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1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2018 Western Digital Corporation or it's affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 : //------------------------------------------------------------------------------------
16 : //
17 : // Copyright Western Digital, 2018
18 : // Owner : Anusha Narayanamoorthy
19 : // Description:
20 : // Wrapper module for JTAG_TAP and DMI synchronizer
21 : //
22 : //-------------------------------------------------------------------------------------
23 :
24 : module dmi_wrapper(
25 :
26 : // JTAG signals
27 16 : input trst_n, // JTAG reset
28 1475306 : input tck, // JTAG clock
29 88482 : input tms, // Test mode select
30 115472 : input tdi, // Test Data Input
31 111513 : output tdo, // Test Data Output
32 44226 : output tdoEnable, // Test Data Output enable
33 :
34 : // Processor Signals
35 309 : input core_rst_n, // Core reset
36 115892092 : input core_clk, // Core clock
37 297 : input [31:1] jtag_id, // JTAG ID
38 5121 : input [31:0] rd_data, // 32 bit Read data from Processor
39 3602 : output [31:0] reg_wr_data, // 32 bit Write data to Processor
40 4600 : output [6:0] reg_wr_addr, // 7 bit reg address to Processor
41 16132 : output reg_en, // 1 bit Read enable to Processor
42 6348 : output reg_wr_en, // 1 bit Write enable to Processor
43 0 : output dmi_hard_reset
44 : );
45 :
46 :
47 :
48 :
49 :
50 : //Wire Declaration
51 9800 : wire rd_en;
52 6348 : wire wr_en;
53 0 : wire dmireset;
54 :
55 :
56 : //jtag_tap instantiation
57 : rvjtag_tap i_jtag_tap(
58 : .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
59 : .tck(tck), // dedicated JTAG TCK pad signal
60 : .tms(tms), // dedicated JTAG TMS pad signal
61 : .tdi(tdi), // dedicated JTAG TDI pad signal
62 : .tdo(tdo), // dedicated JTAG TDO pad signal
63 : .tdoEnable(tdoEnable), // enable for TDO pad
64 : .wr_data(reg_wr_data), // 32 bit Write data
65 : .wr_addr(reg_wr_addr), // 7 bit Write address
66 : .rd_en(rd_en), // 1 bit read enable
67 : .wr_en(wr_en), // 1 bit Write enable
68 : .rd_data(rd_data), // 32 bit Read data
69 : .rd_status(2'b0),
70 : .idle(3'h0), // no need to wait to sample data
71 : .dmi_stat(2'b0), // no need to wait or error possible
72 : .version(4'h1), // debug spec 0.13 compliant
73 : .jtag_id(jtag_id),
74 : .dmi_hard_reset(dmi_hard_reset),
75 : .dmi_reset(dmireset)
76 : );
77 :
78 :
79 : // dmi_jtag_to_core_sync instantiation
80 : dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
81 : .wr_en(wr_en), // 1 bit Write enable
82 : .rd_en(rd_en), // 1 bit Read enable
83 :
84 : .rst_n(core_rst_n),
85 : .clk(core_clk),
86 : .reg_en(reg_en), // 1 bit Write interface bit
87 : .reg_wr_en(reg_wr_en) // 1 bit Write enable
88 : );
89 :
90 : endmodule
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