Line data Source code
1 : // DMI core aperture ranges from 0x00 to 0x4F. Addresses starting from 0x50
2 : // and above are considered uncore.
3 :
4 : module dmi_mux (
5 :
6 : // Core access enable
7 448 : input wire core_enable,
8 : // Uncore access enable
9 1 : input wire uncore_enable,
10 :
11 : // DMI upstream
12 17024 : input wire dmi_en,
13 6324 : input wire dmi_wr_en,
14 3 : input wire [ 6:0] dmi_addr,
15 88 : input wire [31:0] dmi_wdata,
16 116 : output wire [31:0] dmi_rdata,
17 :
18 : // DMI downstream for core
19 17016 : output wire dmi_core_en,
20 6320 : output wire dmi_core_wr_en,
21 3 : output wire [ 6:0] dmi_core_addr,
22 88 : output wire [31:0] dmi_core_wdata,
23 115 : input wire [31:0] dmi_core_rdata,
24 :
25 : // DMI downstream for uncore
26 8 : output wire dmi_uncore_en,
27 4 : output wire dmi_uncore_wr_en,
28 3 : output wire [ 6:0] dmi_uncore_addr,
29 88 : output wire [31:0] dmi_uncore_wdata,
30 1 : input wire [31:0] dmi_uncore_rdata
31 : );
32 7 : logic is_uncore_aperture;
33 :
34 : // Uncore address decoder
35 : assign is_uncore_aperture = (dmi_addr[6] & (dmi_addr[5] | dmi_addr[4]));
36 :
37 : // Core signals
38 : assign dmi_core_en = dmi_en & ~is_uncore_aperture & core_enable;
39 : assign dmi_core_wr_en = dmi_wr_en & ~is_uncore_aperture & core_enable;
40 : assign dmi_core_addr = dmi_addr;
41 : assign dmi_core_wdata = dmi_wdata;
42 :
43 : // Uncore signals
44 : assign dmi_uncore_en = dmi_en & is_uncore_aperture & uncore_enable;
45 : assign dmi_uncore_wr_en = dmi_wr_en & is_uncore_aperture & uncore_enable;
46 : assign dmi_uncore_addr = dmi_addr;
47 : assign dmi_uncore_wdata = dmi_wdata;
48 :
49 : // Read mux
50 : assign dmi_rdata = is_uncore_aperture ? dmi_uncore_rdata : dmi_core_rdata;
51 :
52 : endmodule
|
