Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : // Copyright (c) 2023 Antmicro <www.antmicro.com>
4 : //
5 : // Licensed under the Apache License, Version 2.0 (the "License");
6 : // you may not use this file except in compliance with the License.
7 : // You may obtain a copy of the License at
8 : //
9 : // http://www.apache.org/licenses/LICENSE-2.0
10 : //
11 : // Unless required by applicable law or agreed to in writing, software
12 : // distributed under the License is distributed on an "AS IS" BASIS,
13 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 : // See the License for the specific language governing permissions and
15 : // limitations under the License.
16 :
17 : //********************************************************************************
18 : // $Id$
19 : //
20 : // Function: Top wrapper file with el2_veer/mem instantiated inside
21 : // Comments:
22 : //
23 : //********************************************************************************
24 : module el2_veer_wrapper
25 : import el2_pkg::*;
26 : #(
27 : `include "el2_param.vh"
28 : )
29 : (
30 67228897 : input logic clk,
31 299 : input logic rst_l,
32 297 : input logic dbg_rst_l,
33 : // rst_vec is supposed to be tied to constant in the top level
34 : /*pragma coverage off*/
35 : input logic [31:1] rst_vec,
36 : /*pragma coverage on*/
37 4 : input logic nmi_int,
38 : // jtag_id and nmi_vec are supposed to be tied to constants in the top level
39 : /*pragma coverage off*/
40 : input logic [31:1] nmi_vec,
41 : input logic [31:1] jtag_id,
42 : /*pragma coverage on*/
43 :
44 :
45 4538854 : output logic [31:0] trace_rv_i_insn_ip,
46 6021358 : output logic [31:0] trace_rv_i_address_ip,
47 5873252 : output logic trace_rv_i_valid_ip,
48 3444 : output logic trace_rv_i_exception_ip,
49 3368 : output logic [4:0] trace_rv_i_ecause_ip,
50 8 : output logic trace_rv_i_interrupt_ip,
51 697 : output logic [31:0] trace_rv_i_tval_ip,
52 :
53 : // Bus signals
54 : `ifdef RV_BUILD_AXI4
55 : //-------------------------- LSU AXI signals--------------------------
56 : // AXI Write Channels
57 582310 : output logic lsu_axi_awvalid,
58 589678 : input logic lsu_axi_awready,
59 276579 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
60 276908 : output logic [31:0] lsu_axi_awaddr,
61 49866 : output logic [3:0] lsu_axi_awregion,
62 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
63 : /*pragma coverage off*/
64 : output logic [7:0] lsu_axi_awlen,
65 : /*pragma coverage on*/
66 4138 : output logic [2:0] lsu_axi_awsize,
67 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
68 : /*pragma coverage off*/
69 : output logic [1:0] lsu_axi_awburst,
70 : output logic lsu_axi_awlock,
71 : /*pragma coverage on*/
72 1732 : output logic [3:0] lsu_axi_awcache,
73 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
74 : /*pragma coverage off*/
75 : output logic [2:0] lsu_axi_awprot,
76 : output logic [3:0] lsu_axi_awqos,
77 : /*pragma coverage on*/
78 :
79 582310 : output logic lsu_axi_wvalid,
80 589678 : input logic lsu_axi_wready,
81 120087 : output logic [63:0] lsu_axi_wdata,
82 229722 : output logic [7:0] lsu_axi_wstrb,
83 277 : output logic lsu_axi_wlast,
84 :
85 589464 : input logic lsu_axi_bvalid,
86 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
87 : /*pragma coverage off*/
88 : output logic lsu_axi_bready,
89 : /*pragma coverage on*/
90 12 : input logic [1:0] lsu_axi_bresp,
91 158268 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
92 :
93 : // AXI Read Channels
94 561046 : output logic lsu_axi_arvalid,
95 598554 : input logic lsu_axi_arready,
96 276579 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
97 276908 : output logic [31:0] lsu_axi_araddr,
98 49866 : output logic [3:0] lsu_axi_arregion,
99 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
100 : /*pragma coverage off*/
101 : output logic [7:0] lsu_axi_arlen,
102 : /*pragma coverage on*/
103 4138 : output logic [2:0] lsu_axi_arsize,
104 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
105 : /*pragma coverage off*/
106 : output logic [1:0] lsu_axi_arburst,
107 : output logic lsu_axi_arlock,
108 : /*pragma coverage on*/
109 1732 : output logic [3:0] lsu_axi_arcache,
110 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
111 : /*pragma coverage off*/
112 : output logic [2:0] lsu_axi_arprot,
113 : output logic [3:0] lsu_axi_arqos,
114 : /*pragma coverage on*/
115 :
116 598280 : input logic lsu_axi_rvalid,
117 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
118 : /*pragma coverage off*/
119 : output logic lsu_axi_rready,
120 : /*pragma coverage on*/
121 78283 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
122 82818 : input logic [63:0] lsu_axi_rdata,
123 2 : input logic [1:0] lsu_axi_rresp,
124 599504 : input logic lsu_axi_rlast,
125 :
126 : //-------------------------- IFU AXI signals--------------------------
127 : // AXI Write Channels
128 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv
129 : IFU does not use AXI write channel */
130 : /*pragma coverage off*/
131 : output logic ifu_axi_awvalid,
132 : input logic ifu_axi_awready,
133 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
134 : output logic [31:0] ifu_axi_awaddr,
135 : output logic [3:0] ifu_axi_awregion,
136 : output logic [7:0] ifu_axi_awlen,
137 : output logic [2:0] ifu_axi_awsize,
138 : output logic [1:0] ifu_axi_awburst,
139 : output logic ifu_axi_awlock,
140 : output logic [3:0] ifu_axi_awcache,
141 : output logic [2:0] ifu_axi_awprot,
142 : output logic [3:0] ifu_axi_awqos,
143 :
144 : output logic ifu_axi_wvalid,
145 : input logic ifu_axi_wready,
146 : output logic [63:0] ifu_axi_wdata,
147 : output logic [7:0] ifu_axi_wstrb,
148 : output logic ifu_axi_wlast,
149 :
150 : input logic ifu_axi_bvalid,
151 : output logic ifu_axi_bready,
152 : input logic [1:0] ifu_axi_bresp,
153 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
154 : /*pragma coverage on*/
155 :
156 : // AXI Read Channels
157 4126153 : output logic ifu_axi_arvalid,
158 8272171 : input logic ifu_axi_arready,
159 4136044 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
160 4136044 : output logic [31:0] ifu_axi_araddr,
161 477 : output logic [3:0] ifu_axi_arregion,
162 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
163 : /*pragma coverage off*/
164 : output logic [7:0] ifu_axi_arlen,
165 : output logic [2:0] ifu_axi_arsize,
166 : output logic [1:0] ifu_axi_arburst,
167 : output logic ifu_axi_arlock,
168 : output logic [3:0] ifu_axi_arcache,
169 : output logic [2:0] ifu_axi_arprot,
170 : output logic [3:0] ifu_axi_arqos,
171 : /*pragma coverage on*/
172 :
173 8271895 : input logic ifu_axi_rvalid,
174 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
175 : /*pragma coverage off*/
176 : output logic ifu_axi_rready,
177 : /*pragma coverage on*/
178 3094450 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
179 1745262 : input logic [63:0] ifu_axi_rdata,
180 20 : input logic [1:0] ifu_axi_rresp,
181 8271895 : input logic ifu_axi_rlast,
182 :
183 : //-------------------------- SB AXI signals--------------------------
184 : // AXI Write Channels
185 686 : output logic sb_axi_awvalid,
186 686 : input logic sb_axi_awready,
187 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
188 : /*pragma coverage off*/
189 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
190 : /*pragma coverage on*/
191 894 : output logic [31:0] sb_axi_awaddr,
192 111 : output logic [3:0] sb_axi_awregion,
193 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
194 : /*pragma coverage off*/
195 : output logic [7:0] sb_axi_awlen,
196 : /*pragma coverage on*/
197 1326 : output logic [2:0] sb_axi_awsize,
198 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
199 : /*pragma coverage off*/
200 : output logic [1:0] sb_axi_awburst,
201 : output logic sb_axi_awlock,
202 : output logic [3:0] sb_axi_awcache,
203 : output logic [2:0] sb_axi_awprot,
204 : output logic [3:0] sb_axi_awqos,
205 : /*pragma coverage on*/
206 :
207 686 : output logic sb_axi_wvalid,
208 686 : input logic sb_axi_wready,
209 549 : output logic [63:0] sb_axi_wdata,
210 1574 : output logic [7:0] sb_axi_wstrb,
211 277 : output logic sb_axi_wlast,
212 :
213 686 : input logic sb_axi_bvalid,
214 277 : output logic sb_axi_bready,
215 10 : input logic [1:0] sb_axi_bresp,
216 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
217 :
218 : // AXI Read Channels
219 1224 : output logic sb_axi_arvalid,
220 1224 : input logic sb_axi_arready,
221 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
222 : /*pragma coverage off*/
223 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
224 : /*pragma coverage on*/
225 894 : output logic [31:0] sb_axi_araddr,
226 111 : output logic [3:0] sb_axi_arregion,
227 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
228 : /*pragma coverage off*/
229 : output logic [7:0] sb_axi_arlen,
230 : /*pragma coverage on*/
231 1326 : output logic [2:0] sb_axi_arsize,
232 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
233 : /*pragma coverage off*/
234 : output logic [1:0] sb_axi_arburst,
235 : output logic sb_axi_arlock,
236 : output logic [3:0] sb_axi_arcache,
237 : output logic [2:0] sb_axi_arprot,
238 : output logic [3:0] sb_axi_arqos,
239 : /*pragma coverage on*/
240 :
241 1224 : input logic sb_axi_rvalid,
242 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
243 : /*pragma coverage off*/
244 : output logic sb_axi_rready,
245 : /*pragma coverage on*/
246 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
247 205 : input logic [63:0] sb_axi_rdata,
248 0 : input logic [1:0] sb_axi_rresp,
249 1224 : input logic sb_axi_rlast,
250 :
251 : //-------------------------- DMA AXI signals--------------------------
252 : // AXI Write Channels
253 78 : input logic dma_axi_awvalid,
254 287 : output logic dma_axi_awready,
255 : /* exclude signals that are tied to constant value in tb_top.sv */
256 : /*pragma coverage off*/
257 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
258 : /*pragma coverage on*/
259 276908 : input logic [31:0] dma_axi_awaddr,
260 4137 : input logic [2:0] dma_axi_awsize,
261 276 : input logic [2:0] dma_axi_awprot,
262 0 : input logic [7:0] dma_axi_awlen,
263 276 : input logic [1:0] dma_axi_awburst,
264 :
265 :
266 78 : input logic dma_axi_wvalid,
267 277 : output logic dma_axi_wready,
268 120087 : input logic [63:0] dma_axi_wdata,
269 229722 : input logic [7:0] dma_axi_wstrb,
270 276 : input logic dma_axi_wlast,
271 :
272 78 : output logic dma_axi_bvalid,
273 78 : input logic dma_axi_bready,
274 10 : output logic [1:0] dma_axi_bresp,
275 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
276 :
277 : // AXI Read Channels
278 0 : input logic dma_axi_arvalid,
279 277 : output logic dma_axi_arready,
280 : /* exclude signals that are tied to constant value in tb_top.sv */
281 : /*pragma coverage off*/
282 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
283 : /*pragma coverage on*/
284 276908 : input logic [31:0] dma_axi_araddr,
285 4137 : input logic [2:0] dma_axi_arsize,
286 276 : input logic [2:0] dma_axi_arprot,
287 0 : input logic [7:0] dma_axi_arlen,
288 276 : input logic [1:0] dma_axi_arburst,
289 :
290 0 : output logic dma_axi_rvalid,
291 0 : input logic dma_axi_rready,
292 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
293 159 : output logic [63:0] dma_axi_rdata,
294 10 : output logic [1:0] dma_axi_rresp,
295 277 : output logic dma_axi_rlast,
296 : `endif
297 :
298 : `ifdef RV_BUILD_AHB_LITE
299 : //// AHB LITE BUS
300 1085010 : output logic [31:0] haddr,
301 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
302 : /*pragma coverage off*/
303 : output logic [2:0] hburst,
304 : output logic hmastlock,
305 : /*pragma coverage on*/
306 21 : output logic [3:0] hprot,
307 21 : output logic [2:0] hsize,
308 1442507 : output logic [1:0] htrans,
309 0 : output logic hwrite,
310 :
311 : /* exclude signals that are tied to constant value in this file */
312 : /*pragma coverage off*/
313 : input logic [63:0] hrdata,
314 : input logic hready,
315 : input logic hresp,
316 : /*pragma coverage on*/
317 :
318 : // LSU AHB Master
319 105646 : output logic [31:0] lsu_haddr,
320 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
321 : /*pragma coverage off*/
322 : output logic [2:0] lsu_hburst,
323 : output logic lsu_hmastlock,
324 : /*pragma coverage on*/
325 21 : output logic [3:0] lsu_hprot,
326 88287 : output logic [2:0] lsu_hsize,
327 438066 : output logic [1:0] lsu_htrans,
328 88339 : output logic lsu_hwrite,
329 109033 : output logic [63:0] lsu_hwdata,
330 :
331 : /* exclude signals that are tied to constant value in this file */
332 : /*pragma coverage off*/
333 : input logic [63:0] lsu_hrdata,
334 : input logic lsu_hready,
335 : input logic lsu_hresp,
336 : /*pragma coverage on*/
337 : // Debug Syster Bus AHB
338 740 : output logic [31:0] sb_haddr,
339 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
340 : /*pragma coverage off*/
341 : output logic [2:0] sb_hburst,
342 : output logic sb_hmastlock,
343 : /*pragma coverage on*/
344 21 : output logic [3:0] sb_hprot,
345 156 : output logic [2:0] sb_hsize,
346 1962 : output logic [1:0] sb_htrans,
347 404 : output logic sb_hwrite,
348 464 : output logic [63:0] sb_hwdata,
349 :
350 : /* exclude signals that are tied to constant value in this file */
351 : /*pragma coverage off*/
352 : input logic [63:0] sb_hrdata,
353 : input logic sb_hready,
354 : input logic sb_hresp,
355 : /*pragma coverage on*/
356 :
357 : // DMA Slave
358 : /* exclude signals that are tied to constant value in tb_top.sv */
359 : /*pragma coverage off*/
360 : input logic dma_hsel,
361 : input logic [31:0] dma_haddr,
362 : input logic [2:0] dma_hburst,
363 : input logic dma_hmastlock,
364 : input logic [3:0] dma_hprot,
365 : input logic [2:0] dma_hsize,
366 : input logic [1:0] dma_htrans,
367 : input logic dma_hwrite,
368 : input logic [63:0] dma_hwdata,
369 : /*pragma coverage on*/
370 31 : input logic dma_hreadyin,
371 :
372 1 : output logic [63:0] dma_hrdata,
373 31 : output logic dma_hreadyout,
374 0 : output logic dma_hresp,
375 : `endif
376 : // clk ratio signals
377 327 : input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
378 297 : input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
379 297 : input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
380 297 : input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
381 :
382 : // ICCM/DCCM ECC status
383 16 : output logic iccm_ecc_single_error,
384 8 : output logic iccm_ecc_double_error,
385 4 : output logic dccm_ecc_single_error,
386 4 : output logic dccm_ecc_double_error,
387 :
388 : // ICache export interface
389 : el2_mem_if.veer_icache_src el2_icache_export,
390 :
391 3 : input logic timer_int,
392 6 : input logic soft_int,
393 19 : input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
394 :
395 341326 : output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
396 514626 : output logic dec_tlu_perfcnt1,
397 312914 : output logic dec_tlu_perfcnt2,
398 48468 : output logic dec_tlu_perfcnt3,
399 :
400 : // ports added by the soc team
401 3519724 : input logic jtag_tck, // JTAG clk
402 207346 : input logic jtag_tms, // JTAG TMS
403 264340 : input logic jtag_tdi, // JTAG tdi
404 4 : input logic jtag_trst_n, // JTAG Reset
405 293290 : output logic jtag_tdo, // JTAG TDO
406 103664 : output logic jtag_tdoEn, // JTAG Test Data Output enable
407 :
408 : /*pragma coverage off*/
409 : input logic [31:4] core_id,
410 : /*pragma coverage on*/
411 :
412 : // Memory Export Interface
413 : el2_mem_if.veer_sram_src el2_mem_export,
414 :
415 : // external MPC halt/run interface
416 114 : input logic mpc_debug_halt_req, // Async halt request
417 114 : input logic mpc_debug_run_req, // Async run request
418 297 : input logic mpc_reset_run_req, // Run/halt after reset
419 114 : output logic mpc_debug_halt_ack, // Halt ack
420 114 : output logic mpc_debug_run_ack, // Run ack
421 2 : output logic debug_brkpt_status, // debug breakpoint
422 :
423 114 : input logic i_cpu_halt_req, // Async halt req to CPU
424 114 : output logic o_cpu_halt_ack, // core response to halt
425 114 : output logic o_cpu_halt_status, // 1'b1 indicates core is halted
426 126 : output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
427 114 : input logic i_cpu_run_req, // Async restart req to CPU
428 114 : output logic o_cpu_run_ack, // Core response to run req
429 :
430 : // Excluding scan_mode and mbist_mode from coverage as their usage is determined by the integrator of the VeeR core.
431 : /* pragma coverage off */
432 : input logic scan_mode, // To enable scan mode
433 : input logic mbist_mode, // to enable mbist
434 :
435 : // DMI port for uncore
436 : input logic dmi_core_enable,
437 : input logic dmi_uncore_enable,
438 : output logic dmi_uncore_en,
439 : output logic dmi_uncore_wr_en,
440 : output logic [ 6:0] dmi_uncore_addr,
441 : output logic [31:0] dmi_uncore_wdata,
442 : input logic [31:0] dmi_uncore_rdata,
443 : output logic dmi_active
444 : /* pragma coverage on */
445 : );
446 :
447 67228897 : logic active_l2clk;
448 67228897 : logic free_l2clk;
449 :
450 : // DCCM ports
451 263456 : logic dccm_wren;
452 562308 : logic dccm_rden;
453 169602 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo;
454 169578 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi;
455 1693320 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo;
456 1836218 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi;
457 168982 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo;
458 168982 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi;
459 :
460 394482 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;
461 394484 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;
462 :
463 : // PIC ports
464 :
465 : // Icache & Itag ports
466 6313917 : logic [31:1] ic_rw_addr;
467 15232 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en ; // Which way to write
468 696167 : logic ic_rd_en ;
469 :
470 :
471 691162 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid; // Valid from the I$ tag valid outside (in flops).
472 :
473 622480 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit; // ic_rd_hit[3:0]
474 6 : logic ic_tag_perr; // Ic tag parity error
475 :
476 50 : logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr; // Read/Write addresss to the Icache.
477 20 : logic ic_debug_rd_en; // Icache debug rd
478 100 : logic ic_debug_wr_en; // Icache debug wr
479 8 : logic ic_debug_tag_array; // Debug tag array
480 300 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way; // Debug way. Rd or Wr.
481 :
482 0 : logic [25:0] ictag_debug_rd_data; // Debug icache tag.
483 1665675 : logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
484 7885928 : logic [63:0] ic_rd_data;
485 922010 : logic [70:0] ic_debug_rd_data; // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
486 10 : logic [70:0] ic_debug_wr_data; // Debug wr cache.
487 :
488 0 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr; // ecc error per bank
489 0 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr; // parity error per bank
490 :
491 5149063 : logic [63:0] ic_premux_data;
492 5305334 : logic ic_sel_premux_data;
493 :
494 : // ICCM ports
495 6314085 : logic [pt.ICCM_BITS-1:1] iccm_rw_addr;
496 184 : logic iccm_wren;
497 133250 : logic iccm_rden;
498 198 : logic [2:0] iccm_wr_size;
499 324 : logic [77:0] iccm_wr_data;
500 16 : logic iccm_buf_correct_ecc;
501 16 : logic iccm_correction_state;
502 :
503 906153 : logic [63:0] iccm_rd_data;
504 916708 : logic [77:0] iccm_rd_data_ecc;
505 :
506 299 : logic core_rst_l; // Core reset including rst_l and dbg_rst_l
507 :
508 2 : logic dccm_clk_override;
509 2 : logic icm_clk_override;
510 8 : logic dec_tlu_core_ecc_disable;
511 :
512 :
513 : // zero out the signals not presented at the wrapper instantiation level
514 : `ifdef RV_BUILD_AXI4
515 : // Since all the signals in this block are tied to constant, we exclude this from coverage analysis
516 : /*pragma coverage off*/
517 :
518 : //// AHB LITE BUS
519 : logic [31:0] haddr;
520 : logic [2:0] hburst;
521 : logic hmastlock;
522 : logic [3:0] hprot;
523 : logic [2:0] hsize;
524 : logic [1:0] htrans;
525 : logic hwrite;
526 :
527 : logic [63:0] hrdata;
528 : logic hready;
529 : logic hresp;
530 :
531 : // LSU AHB Master
532 : logic [31:0] lsu_haddr;
533 : logic [2:0] lsu_hburst;
534 : logic lsu_hmastlock;
535 : logic [3:0] lsu_hprot;
536 : logic [2:0] lsu_hsize;
537 : logic [1:0] lsu_htrans;
538 : logic lsu_hwrite;
539 : logic [63:0] lsu_hwdata;
540 :
541 : logic [63:0] lsu_hrdata;
542 : logic lsu_hready;
543 : logic lsu_hresp;
544 : // Debug Syster Bus AHB
545 : logic [31:0] sb_haddr;
546 : logic [2:0] sb_hburst;
547 : logic sb_hmastlock;
548 : logic [3:0] sb_hprot;
549 : logic [2:0] sb_hsize;
550 : logic [1:0] sb_htrans;
551 : logic sb_hwrite;
552 : logic [63:0] sb_hwdata;
553 :
554 : logic [63:0] sb_hrdata;
555 : logic sb_hready;
556 : logic sb_hresp;
557 :
558 : // DMA Slave
559 : logic dma_hsel;
560 : logic [31:0] dma_haddr;
561 : logic [2:0] dma_hburst;
562 : logic dma_hmastlock;
563 : logic [3:0] dma_hprot;
564 : logic [2:0] dma_hsize;
565 : logic [1:0] dma_htrans;
566 : logic dma_hwrite;
567 : logic [63:0] dma_hwdata;
568 : logic dma_hreadyin;
569 :
570 : logic [63:0] dma_hrdata;
571 : logic dma_hreadyout;
572 : logic dma_hresp;
573 :
574 :
575 :
576 : // AHB
577 : assign hrdata[63:0] = '0;
578 : assign hready = '0;
579 : assign hresp = '0;
580 : // LSU
581 : assign lsu_hrdata[63:0] = '0;
582 : assign lsu_hready = '0;
583 : assign lsu_hresp = '0;
584 : // Debu
585 : assign sb_hrdata[63:0] = '0;
586 : assign sb_hready = '0;
587 : assign sb_hresp = '0;
588 :
589 : // DMA
590 : assign dma_hsel = '0;
591 : assign dma_haddr[31:0] = '0;
592 : assign dma_hburst[2:0] = '0;
593 : assign dma_hmastlock = '0;
594 : assign dma_hprot[3:0] = '0;
595 : assign dma_hsize[2:0] = '0;
596 : assign dma_htrans[1:0] = '0;
597 : assign dma_hwrite = '0;
598 : assign dma_hwdata[63:0] = '0;
599 : assign dma_hreadyin = '0;
600 :
601 : /*pragma coverage on*/
602 :
603 : `endif // `ifdef RV_BUILD_AXI4
604 :
605 :
606 : `ifdef RV_BUILD_AHB_LITE
607 : // Since all the signals in this block are tied to constant, we exclude this from coverage analysis
608 : /*pragma coverage off*/
609 : wire lsu_axi_awvalid;
610 : wire lsu_axi_awready;
611 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;
612 : wire [31:0] lsu_axi_awaddr;
613 : wire [3:0] lsu_axi_awregion;
614 : wire [7:0] lsu_axi_awlen;
615 : wire [2:0] lsu_axi_awsize;
616 : wire [1:0] lsu_axi_awburst;
617 : wire lsu_axi_awlock;
618 : wire [3:0] lsu_axi_awcache;
619 : wire [2:0] lsu_axi_awprot;
620 : wire [3:0] lsu_axi_awqos;
621 :
622 :
623 : wire lsu_axi_wvalid;
624 : wire lsu_axi_wready;
625 : wire [63:0] lsu_axi_wdata;
626 : wire [7:0] lsu_axi_wstrb;
627 : wire lsu_axi_wlast;
628 :
629 : wire lsu_axi_bvalid;
630 : wire lsu_axi_bready;
631 : wire [1:0] lsu_axi_bresp;
632 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;
633 :
634 : // AXI Read Channels
635 : wire lsu_axi_arvalid;
636 : wire lsu_axi_arready;
637 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;
638 : wire [31:0] lsu_axi_araddr;
639 : wire [3:0] lsu_axi_arregion;
640 : wire [7:0] lsu_axi_arlen;
641 : wire [2:0] lsu_axi_arsize;
642 : wire [1:0] lsu_axi_arburst;
643 : wire lsu_axi_arlock;
644 : wire [3:0] lsu_axi_arcache;
645 : wire [2:0] lsu_axi_arprot;
646 : wire [3:0] lsu_axi_arqos;
647 :
648 : wire lsu_axi_rvalid;
649 : wire lsu_axi_rready;
650 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;
651 : wire [63:0] lsu_axi_rdata;
652 : wire [1:0] lsu_axi_rresp;
653 : wire lsu_axi_rlast;
654 :
655 : assign lsu_axi_awready = '0;
656 : assign lsu_axi_wready = '0;
657 : assign lsu_axi_bvalid = '0;
658 : assign lsu_axi_bresp = '0;
659 : assign lsu_axi_bid = {pt.LSU_BUS_TAG{1'b0}};
660 : assign lsu_axi_arready = '0;
661 : assign lsu_axi_rvalid = '0;
662 : assign lsu_axi_rid = {pt.LSU_BUS_TAG{1'b0}};
663 : assign lsu_axi_rdata = '0;
664 : assign lsu_axi_rresp = '0;
665 : assign lsu_axi_rlast = '0;
666 : //-------------------------- IFU AXI signals--------------------------
667 : // AXI Write Channels
668 : wire ifu_axi_awvalid;
669 : wire ifu_axi_awready;
670 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;
671 : wire [31:0] ifu_axi_awaddr;
672 : wire [3:0] ifu_axi_awregion;
673 : wire [7:0] ifu_axi_awlen;
674 : wire [2:0] ifu_axi_awsize;
675 : wire [1:0] ifu_axi_awburst;
676 : wire ifu_axi_awlock;
677 : wire [3:0] ifu_axi_awcache;
678 : wire [2:0] ifu_axi_awprot;
679 : wire [3:0] ifu_axi_awqos;
680 :
681 : wire ifu_axi_wvalid;
682 : wire ifu_axi_wready;
683 : wire [63:0] ifu_axi_wdata;
684 : wire [7:0] ifu_axi_wstrb;
685 : wire ifu_axi_wlast;
686 :
687 : wire ifu_axi_bvalid;
688 : wire ifu_axi_bready;
689 : wire [1:0] ifu_axi_bresp;
690 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_bid;
691 :
692 : // AXI Read Channels
693 : wire ifu_axi_arvalid;
694 : wire ifu_axi_arready;
695 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_arid;
696 : wire [31:0] ifu_axi_araddr;
697 : wire [3:0] ifu_axi_arregion;
698 : wire [7:0] ifu_axi_arlen;
699 : wire [2:0] ifu_axi_arsize;
700 : wire [1:0] ifu_axi_arburst;
701 : wire ifu_axi_arlock;
702 : wire [3:0] ifu_axi_arcache;
703 : wire [2:0] ifu_axi_arprot;
704 : wire [3:0] ifu_axi_arqos;
705 :
706 : wire ifu_axi_rvalid;
707 : wire ifu_axi_rready;
708 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_rid;
709 : wire [63:0] ifu_axi_rdata;
710 : wire [1:0] ifu_axi_rresp;
711 : wire ifu_axi_rlast;
712 :
713 : assign ifu_axi_bvalid = '0;
714 : assign ifu_axi_bresp = '0;
715 : assign ifu_axi_bid = {pt.IFU_BUS_TAG{1'b0}};
716 : assign ifu_axi_arready = '0;
717 : assign ifu_axi_rvalid = '0;
718 : assign ifu_axi_rid = {pt.IFU_BUS_TAG{1'b0}};
719 : assign ifu_axi_rdata = 0;
720 : assign ifu_axi_rresp = '0;
721 : assign ifu_axi_rlast = '0;
722 : //-------------------------- SB AXI signals--------------------------
723 : // AXI Write Channels
724 : wire sb_axi_awvalid;
725 : wire sb_axi_awready;
726 : wire [pt.SB_BUS_TAG-1:0] sb_axi_awid;
727 : wire [31:0] sb_axi_awaddr;
728 : wire [3:0] sb_axi_awregion;
729 : wire [7:0] sb_axi_awlen;
730 : wire [2:0] sb_axi_awsize;
731 : wire [1:0] sb_axi_awburst;
732 : wire sb_axi_awlock;
733 : wire [3:0] sb_axi_awcache;
734 : wire [2:0] sb_axi_awprot;
735 : wire [3:0] sb_axi_awqos;
736 :
737 : wire sb_axi_wvalid;
738 : wire sb_axi_wready;
739 : wire [63:0] sb_axi_wdata;
740 : wire [7:0] sb_axi_wstrb;
741 : wire sb_axi_wlast;
742 :
743 : wire sb_axi_bvalid;
744 : wire sb_axi_bready;
745 : wire [1:0] sb_axi_bresp;
746 : wire [pt.SB_BUS_TAG-1:0] sb_axi_bid;
747 :
748 : // AXI Read Channels
749 : wire sb_axi_arvalid;
750 : wire sb_axi_arready;
751 : wire [pt.SB_BUS_TAG-1:0] sb_axi_arid;
752 : wire [31:0] sb_axi_araddr;
753 : wire [3:0] sb_axi_arregion;
754 : wire [7:0] sb_axi_arlen;
755 : wire [2:0] sb_axi_arsize;
756 : wire [1:0] sb_axi_arburst;
757 : wire sb_axi_arlock;
758 : wire [3:0] sb_axi_arcache;
759 : wire [2:0] sb_axi_arprot;
760 : wire [3:0] sb_axi_arqos;
761 :
762 : wire sb_axi_rvalid;
763 : wire sb_axi_rready;
764 : wire [pt.SB_BUS_TAG-1:0] sb_axi_rid;
765 : wire [63:0] sb_axi_rdata;
766 : wire [1:0] sb_axi_rresp;
767 : wire sb_axi_rlast;
768 :
769 : assign sb_axi_awready = '0;
770 : assign sb_axi_wready = '0;
771 : assign sb_axi_bvalid = '0;
772 : assign sb_axi_bresp = '0;
773 : assign sb_axi_bid = {pt.SB_BUS_TAG{1'b0}};
774 : assign sb_axi_arready = '0;
775 : assign sb_axi_rvalid = '0;
776 : assign sb_axi_rid = {pt.SB_BUS_TAG{1'b0}};
777 : assign sb_axi_rdata = '0;
778 : assign sb_axi_rresp = '0;
779 : assign sb_axi_rlast = '0;
780 : //-------------------------- DMA AXI signals--------------------------
781 : // AXI Write Channels
782 : wire dma_axi_awvalid;
783 : wire dma_axi_awready;
784 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_awid;
785 : wire [31:0] dma_axi_awaddr;
786 : wire [2:0] dma_axi_awsize;
787 : wire [2:0] dma_axi_awprot;
788 : wire [7:0] dma_axi_awlen;
789 : wire [1:0] dma_axi_awburst;
790 :
791 :
792 : wire dma_axi_wvalid;
793 : wire dma_axi_wready;
794 : wire [63:0] dma_axi_wdata;
795 : wire [7:0] dma_axi_wstrb;
796 : wire dma_axi_wlast;
797 :
798 : assign dma_axi_awvalid = 1'b0;
799 : assign dma_axi_awid = {pt.DMA_BUS_TAG{1'b0}};
800 : assign dma_axi_awaddr = 32'd0;
801 : assign dma_axi_awsize = 3'd0;
802 : assign dma_axi_awprot = 3'd0;
803 : assign dma_axi_awlen = 8'd0;
804 : assign dma_axi_awburst = 2'd0;
805 :
806 :
807 : assign dma_axi_wvalid = 1'b0;
808 : assign dma_axi_wdata = 64'd0;
809 : assign dma_axi_wstrb = 8'd0;
810 : assign dma_axi_wlast = 1'b0;
811 :
812 :
813 : wire dma_axi_bvalid;
814 : wire dma_axi_bready;
815 : wire [1:0] dma_axi_bresp;
816 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_bid;
817 :
818 : assign dma_axi_bready = 1'b0;
819 : // AXI Read Channels
820 : wire dma_axi_arvalid;
821 : wire dma_axi_arready;
822 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_arid;
823 : wire [31:0] dma_axi_araddr;
824 : wire [2:0] dma_axi_arsize;
825 : wire [2:0] dma_axi_arprot;
826 : wire [7:0] dma_axi_arlen;
827 : wire [1:0] dma_axi_arburst;
828 :
829 : assign dma_axi_arvalid = 1'b0;
830 : assign dma_axi_arid = {pt.DMA_BUS_TAG{1'b0}};
831 : assign dma_axi_araddr = 32'd0;
832 : assign dma_axi_arsize = 3'd0;
833 : assign dma_axi_arprot = 3'd0;
834 : assign dma_axi_arlen = 8'd0;
835 : assign dma_axi_arburst = 2'd0;
836 :
837 :
838 :
839 : wire dma_axi_rvalid;
840 : wire dma_axi_rready;
841 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_rid;
842 : wire [63:0] dma_axi_rdata;
843 : wire [1:0] dma_axi_rresp;
844 : wire dma_axi_rlast;
845 :
846 : assign dma_axi_rready = 1'b0;
847 : // AXI
848 : assign ifu_axi_awready = 1'b1;
849 : assign ifu_axi_wready = 1'b1;
850 : assign ifu_axi_bvalid = '0;
851 : assign ifu_axi_bresp[1:0] = '0;
852 : assign ifu_axi_bid[pt.IFU_BUS_TAG-1:0] = '0;
853 :
854 : /*pragma coverage on*/
855 :
856 : `endif // `ifdef RV_BUILD_AHB_LITE
857 :
858 : // DMI (core)
859 37058 : logic dmi_en;
860 11856 : logic [6:0] dmi_addr;
861 16732 : logic dmi_wr_en;
862 7148 : logic [31:0] dmi_wdata;
863 11462 : logic [31:0] dmi_rdata;
864 :
865 : // DMI (core)
866 37058 : logic dmi_reg_en;
867 11856 : logic [6:0] dmi_reg_addr;
868 16732 : logic dmi_reg_wr_en;
869 7148 : logic [31:0] dmi_reg_wdata;
870 11462 : logic [31:0] dmi_reg_rdata;
871 :
872 : // Instantiate the el2_veer core
873 : el2_veer #(.pt(pt)) veer (
874 : .clk(clk),
875 : .*
876 : );
877 :
878 : // Instantiate the mem
879 : el2_mem #(.pt(pt)) mem (
880 : .clk(active_l2clk),
881 : .rst_l(core_rst_l),
882 : .mem_export(el2_mem_export),
883 : .icache_export(el2_icache_export),
884 : .*
885 : );
886 :
887 :
888 : // JTAG/DMI instance
889 : dmi_wrapper dmi_wrapper (
890 : // JTAG signals
891 : .trst_n (jtag_trst_n), // JTAG reset
892 : .tck (jtag_tck), // JTAG clock
893 : .tms (jtag_tms), // Test mode select
894 : .tdi (jtag_tdi), // Test Data Input
895 : .tdo (jtag_tdo), // Test Data Output
896 : .tdoEnable (jtag_tdoEn), // Test Data Output enable
897 : // Processor Signals
898 : .core_rst_n (dbg_rst_l), // Debug reset, active low
899 : .core_clk (clk), // Core clock
900 : .jtag_id (jtag_id), // JTAG ID
901 : .rd_data (dmi_rdata), // Read data from Processor
902 : .reg_wr_data (dmi_wdata), // Write data to Processor
903 : .reg_wr_addr (dmi_addr), // Write address to Processor
904 : .reg_en (dmi_en), // Write interface bit to Processor
905 : .reg_wr_en (dmi_wr_en), // Write enable to Processor
906 : .dmi_hard_reset ()
907 : );
908 :
909 : // DMI core/uncore mux
910 : dmi_mux dmi_mux (
911 : .core_enable (dmi_core_enable),
912 : .uncore_enable (dmi_uncore_enable),
913 :
914 : .dmi_en (dmi_en),
915 : .dmi_wr_en (dmi_wr_en),
916 : .dmi_addr (dmi_addr),
917 : .dmi_wdata (dmi_wdata),
918 : .dmi_rdata (dmi_rdata),
919 :
920 : .dmi_core_en (dmi_reg_en),
921 : .dmi_core_wr_en (dmi_reg_wr_en),
922 : .dmi_core_addr (dmi_reg_addr),
923 : .dmi_core_wdata (dmi_reg_wdata),
924 : .dmi_core_rdata (dmi_reg_rdata),
925 :
926 : .dmi_uncore_en (dmi_uncore_en),
927 : .dmi_uncore_wr_en (dmi_uncore_wr_en),
928 : .dmi_uncore_addr (dmi_uncore_addr),
929 : .dmi_uncore_wdata (dmi_uncore_wdata),
930 : .dmi_uncore_rdata (dmi_uncore_rdata)
931 : );
932 :
933 298 : always_comb dmi_active = dmi_en;
934 :
935 : `ifdef RV_ASSERT_ON
936 : // to avoid internal assertions failure at time 0
937 : initial begin
938 : $assertoff(0, veer);
939 : @(negedge clk) $asserton(0, veer);
940 : end
941 : `endif
942 :
943 : endmodule
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