Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 : //********************************************************************************
17 : // $Id$
18 : //
19 : // Function: Top level VeeR core file
20 : // Comments:
21 : //
22 : //********************************************************************************
23 : module el2_veer
24 : import el2_pkg::*;
25 : #(
26 : `include "el2_param.vh"
27 : )
28 : (
29 115209064 : input logic clk,
30 299 : input logic rst_l,
31 297 : input logic dbg_rst_l,
32 297 : input logic [31:1] rst_vec,
33 15 : input logic nmi_int,
34 313 : input logic [31:1] nmi_vec,
35 299 : output logic core_rst_l, // This is "rst_l | dbg_rst_l"
36 :
37 115209064 : output logic active_l2clk,
38 115209064 : output logic free_l2clk,
39 :
40 5682988 : output logic [31:0] trace_rv_i_insn_ip,
41 7003720 : output logic [31:0] trace_rv_i_address_ip,
42 9541475 : output logic trace_rv_i_valid_ip,
43 1234814 : output logic trace_rv_i_exception_ip,
44 1234764 : output logic [4:0] trace_rv_i_ecause_ip,
45 32 : output logic trace_rv_i_interrupt_ip,
46 114141 : output logic [31:0] trace_rv_i_tval_ip,
47 :
48 :
49 2 : output logic dccm_clk_override,
50 2 : output logic icm_clk_override,
51 8 : output logic dec_tlu_core_ecc_disable,
52 :
53 : // external halt/run interface
54 114 : input logic i_cpu_halt_req, // Asynchronous Halt request to CPU
55 114 : input logic i_cpu_run_req, // Asynchronous Restart request to CPU
56 114 : output logic o_cpu_halt_ack, // Core Acknowledge to Halt request
57 114 : output logic o_cpu_halt_status, // 1'b1 indicates processor is halted
58 114 : output logic o_cpu_run_ack, // Core Acknowledge to run request
59 124 : output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
60 :
61 0 : input logic [31:4] core_id, // CORE ID
62 :
63 : // external MPC halt/run interface
64 114 : input logic mpc_debug_halt_req, // Async halt request
65 114 : input logic mpc_debug_run_req, // Async run request
66 297 : input logic mpc_reset_run_req, // Run/halt after reset
67 114 : output logic mpc_debug_halt_ack, // Halt ack
68 114 : output logic mpc_debug_run_ack, // Run ack
69 2 : output logic debug_brkpt_status, // debug breakpoint
70 :
71 170342 : output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
72 257346 : output logic dec_tlu_perfcnt1,
73 156466 : output logic dec_tlu_perfcnt2,
74 24234 : output logic dec_tlu_perfcnt3,
75 :
76 : // DCCM ports
77 273904 : output logic dccm_wren,
78 620164 : output logic dccm_rden,
79 173860 : output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
80 173860 : output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
81 2125408 : output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
82 2449739 : output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
83 174952 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
84 174952 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
85 :
86 429168 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
87 429168 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
88 :
89 : // ICCM ports
90 8818338 : output logic [pt.ICCM_BITS-1:1] iccm_rw_addr,
91 124 : output logic iccm_wren,
92 133490 : output logic iccm_rden,
93 108 : output logic [2:0] iccm_wr_size,
94 66 : output logic [77:0] iccm_wr_data,
95 16 : output logic iccm_buf_correct_ecc,
96 16 : output logic iccm_correction_state,
97 :
98 569299 : input logic [63:0] iccm_rd_data,
99 583846 : input logic [77:0] iccm_rd_data_ecc,
100 :
101 : // ICache , ITAG ports
102 9477817 : output logic [31:1] ic_rw_addr,
103 1837394 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,
104 1182559 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,
105 1802803 : output logic ic_rd_en,
106 :
107 3505602 : output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
108 10070696 : input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
109 29201 : input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
110 0 : input logic [25:0] ictag_debug_rd_data,// Debug icache tag.
111 10 : output logic [70:0] ic_debug_wr_data, // Debug wr cache.
112 :
113 6 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
114 0 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
115 8455501 : output logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
116 9100770 : output logic ic_sel_premux_data, // Select premux data
117 :
118 :
119 50 : output logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
120 20 : output logic ic_debug_rd_en, // Icache debug rd
121 100 : output logic ic_debug_wr_en, // Icache debug wr
122 8 : output logic ic_debug_tag_array, // Debug tag array
123 300 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
124 :
125 :
126 :
127 16003 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
128 0 : input logic ic_tag_perr, // Icache Tag parity error
129 :
130 : //-------------------------- LSU AXI signals--------------------------
131 : // AXI Write Channels
132 895815 : output logic lsu_axi_awvalid,
133 581962 : input logic lsu_axi_awready,
134 682811 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
135 568021 : output logic [31:0] lsu_axi_awaddr,
136 139839 : output logic [3:0] lsu_axi_awregion,
137 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
138 : /*pragma coverage off*/
139 : output logic [7:0] lsu_axi_awlen,
140 : /*pragma coverage on*/
141 3043 : output logic [2:0] lsu_axi_awsize,
142 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
143 : /*pragma coverage off*/
144 : output logic [1:0] lsu_axi_awburst,
145 : output logic lsu_axi_awlock,
146 : /*pragma coverage on*/
147 1957 : output logic [3:0] lsu_axi_awcache,
148 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
149 : /*pragma coverage off*/
150 : output logic [2:0] lsu_axi_awprot,
151 : output logic [3:0] lsu_axi_awqos,
152 : /*pragma coverage on*/
153 :
154 895815 : output logic lsu_axi_wvalid,
155 581962 : input logic lsu_axi_wready,
156 226222 : output logic [63:0] lsu_axi_wdata,
157 409701 : output logic [7:0] lsu_axi_wstrb,
158 298 : output logic lsu_axi_wlast,
159 :
160 581752 : input logic lsu_axi_bvalid,
161 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
162 : /*pragma coverage off*/
163 : output logic lsu_axi_bready,
164 : /*pragma coverage on*/
165 2 : input logic [1:0] lsu_axi_bresp,
166 151547 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
167 :
168 : // AXI Read Channels
169 1046836 : output logic lsu_axi_arvalid,
170 599034 : input logic lsu_axi_arready,
171 682811 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
172 568021 : output logic [31:0] lsu_axi_araddr,
173 139839 : output logic [3:0] lsu_axi_arregion,
174 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
175 : /*pragma coverage off*/
176 : output logic [7:0] lsu_axi_arlen,
177 : /*pragma coverage on*/
178 3043 : output logic [2:0] lsu_axi_arsize,
179 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
180 : /*pragma coverage off*/
181 : output logic [1:0] lsu_axi_arburst,
182 : output logic lsu_axi_arlock,
183 : /*pragma coverage on*/
184 1957 : output logic [3:0] lsu_axi_arcache,
185 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
186 : /*pragma coverage off*/
187 : output logic [2:0] lsu_axi_arprot,
188 : output logic [3:0] lsu_axi_arqos,
189 : /*pragma coverage on*/
190 :
191 598760 : input logic lsu_axi_rvalid,
192 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
193 : /*pragma coverage off*/
194 : output logic lsu_axi_rready,
195 : /*pragma coverage on*/
196 77456 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
197 82926 : input logic [63:0] lsu_axi_rdata,
198 2 : input logic [1:0] lsu_axi_rresp,
199 599412 : input logic lsu_axi_rlast,
200 :
201 : //-------------------------- IFU AXI signals--------------------------
202 : // AXI Write Channels
203 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv
204 : IFU does not use AXI write channel */
205 : /*pragma coverage off*/
206 : output logic ifu_axi_awvalid,
207 : input logic ifu_axi_awready,
208 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
209 : output logic [31:0] ifu_axi_awaddr,
210 : output logic [3:0] ifu_axi_awregion,
211 : output logic [7:0] ifu_axi_awlen,
212 : output logic [2:0] ifu_axi_awsize,
213 : output logic [1:0] ifu_axi_awburst,
214 : output logic ifu_axi_awlock,
215 : output logic [3:0] ifu_axi_awcache,
216 : output logic [2:0] ifu_axi_awprot,
217 : output logic [3:0] ifu_axi_awqos,
218 :
219 : output logic ifu_axi_wvalid,
220 : input logic ifu_axi_wready,
221 : output logic [63:0] ifu_axi_wdata,
222 : output logic [7:0] ifu_axi_wstrb,
223 : output logic ifu_axi_wlast,
224 :
225 : input logic ifu_axi_bvalid,
226 : output logic ifu_axi_bready,
227 : input logic [1:0] ifu_axi_bresp,
228 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
229 : /*pragma coverage on*/
230 :
231 : // AXI Read Channels
232 9410024 : output logic ifu_axi_arvalid,
233 10913445 : input logic ifu_axi_arready,
234 11181859 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
235 11181859 : output logic [31:0] ifu_axi_araddr,
236 6431 : output logic [3:0] ifu_axi_arregion,
237 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
238 : /*pragma coverage off*/
239 : output logic [7:0] ifu_axi_arlen,
240 : output logic [2:0] ifu_axi_arsize,
241 : output logic [1:0] ifu_axi_arburst,
242 : output logic ifu_axi_arlock,
243 : output logic [3:0] ifu_axi_arcache,
244 : output logic [2:0] ifu_axi_arprot,
245 : output logic [3:0] ifu_axi_arqos,
246 : /*pragma coverage on*/
247 :
248 10913169 : input logic ifu_axi_rvalid,
249 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
250 : /*pragma coverage off*/
251 : output logic ifu_axi_rready,
252 : /*pragma coverage on*/
253 4354048 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
254 2391697 : input logic [63:0] ifu_axi_rdata,
255 2 : input logic [1:0] ifu_axi_rresp,
256 10913169 : input logic ifu_axi_rlast,
257 :
258 : //-------------------------- SB AXI signals--------------------------
259 : // AXI Write Channels
260 244 : output logic sb_axi_awvalid,
261 122 : input logic sb_axi_awready,
262 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
263 : /*pragma coverage off*/
264 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
265 : /*pragma coverage on*/
266 772 : output logic [31:0] sb_axi_awaddr,
267 198 : output logic [3:0] sb_axi_awregion,
268 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
269 : /*pragma coverage off*/
270 : output logic [7:0] sb_axi_awlen,
271 : /*pragma coverage on*/
272 1228 : output logic [2:0] sb_axi_awsize,
273 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
274 : /*pragma coverage off*/
275 : output logic [1:0] sb_axi_awburst,
276 : output logic sb_axi_awlock,
277 : output logic [3:0] sb_axi_awcache,
278 : output logic [2:0] sb_axi_awprot,
279 : output logic [3:0] sb_axi_awqos,
280 : /*pragma coverage on*/
281 :
282 244 : output logic sb_axi_wvalid,
283 122 : input logic sb_axi_wready,
284 178 : output logic [63:0] sb_axi_wdata,
285 1304 : output logic [7:0] sb_axi_wstrb,
286 298 : output logic sb_axi_wlast,
287 :
288 122 : input logic sb_axi_bvalid,
289 298 : output logic sb_axi_bready,
290 0 : input logic [1:0] sb_axi_bresp,
291 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
292 :
293 : // AXI Read Channels
294 1272 : output logic sb_axi_arvalid,
295 652 : input logic sb_axi_arready,
296 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
297 : /*pragma coverage off*/
298 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
299 : /*pragma coverage on*/
300 772 : output logic [31:0] sb_axi_araddr,
301 198 : output logic [3:0] sb_axi_arregion,
302 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
303 : /*pragma coverage off*/
304 : output logic [7:0] sb_axi_arlen,
305 : /*pragma coverage on*/
306 1228 : output logic [2:0] sb_axi_arsize,
307 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
308 : /*pragma coverage off*/
309 : output logic [1:0] sb_axi_arburst,
310 : output logic sb_axi_arlock,
311 : output logic [3:0] sb_axi_arcache,
312 : output logic [2:0] sb_axi_arprot,
313 : output logic [3:0] sb_axi_arqos,
314 : /*pragma coverage on*/
315 :
316 652 : input logic sb_axi_rvalid,
317 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
318 : /*pragma coverage off*/
319 : output logic sb_axi_rready,
320 : /*pragma coverage on*/
321 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
322 294 : input logic [63:0] sb_axi_rdata,
323 0 : input logic [1:0] sb_axi_rresp,
324 652 : input logic sb_axi_rlast,
325 :
326 : //-------------------------- DMA AXI signals--------------------------
327 : // AXI Write Channels
328 68 : input logic dma_axi_awvalid,
329 298 : output logic dma_axi_awready,
330 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
331 276858 : input logic [31:0] dma_axi_awaddr,
332 2243 : input logic [2:0] dma_axi_awsize,
333 276 : input logic [2:0] dma_axi_awprot,
334 0 : input logic [7:0] dma_axi_awlen,
335 276 : input logic [1:0] dma_axi_awburst,
336 :
337 :
338 68 : input logic dma_axi_wvalid,
339 298 : output logic dma_axi_wready,
340 119774 : input logic [63:0] dma_axi_wdata,
341 228147 : input logic [7:0] dma_axi_wstrb,
342 276 : input logic dma_axi_wlast,
343 :
344 108 : output logic dma_axi_bvalid,
345 68 : input logic dma_axi_bready,
346 4 : output logic [1:0] dma_axi_bresp,
347 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
348 :
349 : // AXI Read Channels
350 0 : input logic dma_axi_arvalid,
351 298 : output logic dma_axi_arready,
352 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
353 276858 : input logic [31:0] dma_axi_araddr,
354 2243 : input logic [2:0] dma_axi_arsize,
355 276 : input logic [2:0] dma_axi_arprot,
356 0 : input logic [7:0] dma_axi_arlen,
357 276 : input logic [1:0] dma_axi_arburst,
358 :
359 0 : output logic dma_axi_rvalid,
360 0 : input logic dma_axi_rready,
361 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
362 52 : output logic [63:0] dma_axi_rdata,
363 4 : output logic [1:0] dma_axi_rresp,
364 298 : output logic dma_axi_rlast,
365 :
366 :
367 : //// AHB LITE BUS
368 5121743 : output logic [31:0] haddr,
369 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
370 : /*pragma coverage off*/
371 : output logic [2:0] hburst,
372 : output logic hmastlock,
373 : /*pragma coverage on*/
374 21 : output logic [3:0] hprot,
375 21 : output logic [2:0] hsize,
376 4953800 : output logic [1:0] htrans,
377 0 : output logic hwrite,
378 :
379 3265315 : input logic [63:0] hrdata,
380 21 : input logic hready,
381 0 : input logic hresp,
382 :
383 : // LSU AHB Master
384 304884 : output logic [31:0] lsu_haddr,
385 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
386 : /*pragma coverage off*/
387 : output logic [2:0] lsu_hburst,
388 : output logic lsu_hmastlock,
389 : /*pragma coverage on*/
390 21 : output logic [3:0] lsu_hprot,
391 105940 : output logic [2:0] lsu_hsize,
392 800804 : output logic [1:0] lsu_htrans,
393 105279 : output logic lsu_hwrite,
394 117802 : output logic [63:0] lsu_hwdata,
395 :
396 22391 : input logic [63:0] lsu_hrdata,
397 484871 : input logic lsu_hready,
398 0 : input logic lsu_hresp,
399 :
400 : //System Bus Debug Master
401 368 : output logic [31:0] sb_haddr,
402 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
403 : /*pragma coverage off*/
404 : output logic [2:0] sb_hburst,
405 : output logic sb_hmastlock,
406 : /*pragma coverage on*/
407 21 : output logic [3:0] sb_hprot,
408 117 : output logic [2:0] sb_hsize,
409 742 : output logic [1:0] sb_htrans,
410 119 : output logic sb_hwrite,
411 296 : output logic [63:0] sb_hwdata,
412 :
413 682 : input logic [63:0] sb_hrdata,
414 622 : input logic sb_hready,
415 0 : input logic sb_hresp,
416 :
417 : // DMA Slave
418 21 : input logic dma_hsel,
419 16 : input logic [31:0] dma_haddr,
420 0 : input logic [2:0] dma_hburst,
421 0 : input logic dma_hmastlock,
422 21 : input logic [3:0] dma_hprot,
423 1 : input logic [2:0] dma_hsize,
424 40 : input logic [1:0] dma_htrans,
425 1 : input logic dma_hwrite,
426 16 : input logic [63:0] dma_hwdata,
427 21 : input logic dma_hreadyin,
428 :
429 0 : output logic [63:0] dma_hrdata,
430 21 : output logic dma_hreadyout,
431 0 : output logic dma_hresp,
432 :
433 327 : input logic lsu_bus_clk_en,
434 297 : input logic ifu_bus_clk_en,
435 297 : input logic dbg_bus_clk_en,
436 297 : input logic dma_bus_clk_en,
437 :
438 16086 : input logic dmi_reg_en, // read or write
439 4588 : input logic [6:0] dmi_reg_addr, // address of DM register
440 6332 : input logic dmi_reg_wr_en, // write instruction
441 3594 : input logic [31:0] dmi_reg_wdata, // write data
442 5106 : output logic [31:0] dmi_reg_rdata,
443 :
444 : // ICCM/DCCM ECC status
445 16 : output logic iccm_ecc_single_error,
446 4 : output logic iccm_ecc_double_error,
447 4 : output logic dccm_ecc_single_error,
448 4 : output logic dccm_ecc_double_error,
449 :
450 21 : input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
451 13 : input logic timer_int,
452 14 : input logic soft_int,
453 : // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
454 : /*pragma coverage off*/
455 : input logic scan_mode
456 : /*pragma coverage on*/
457 : );
458 :
459 :
460 :
461 :
462 3132382 : logic [63:0] hwdata_nc;
463 : //----------------------------------------------------------------------
464 : //
465 : //----------------------------------------------------------------------
466 :
467 9566855 : logic ifu_pmu_instr_aligned;
468 6 : logic ifu_ic_error_start;
469 0 : logic ifu_iccm_dma_rd_ecc_single_err;
470 16 : logic ifu_iccm_rd_ecc_single_err;
471 4 : logic ifu_iccm_rd_ecc_double_err;
472 4 : logic lsu_dccm_rd_ecc_single_err;
473 4 : logic lsu_dccm_rd_ecc_double_err;
474 :
475 806693 : logic lsu_axi_awready_ahb;
476 806693 : logic lsu_axi_wready_ahb;
477 321814 : logic lsu_axi_bvalid_ahb;
478 0 : logic lsu_axi_bready_ahb;
479 0 : logic [1:0] lsu_axi_bresp_ahb;
480 242800 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_ahb;
481 806053 : logic lsu_axi_arready_ahb;
482 484850 : logic lsu_axi_rvalid_ahb;
483 242800 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_ahb;
484 22391 : logic [63:0] lsu_axi_rdata_ahb;
485 0 : logic [1:0] lsu_axi_rresp_ahb;
486 21 : logic lsu_axi_rlast_ahb;
487 :
488 1388655 : logic lsu_axi_awready_int;
489 1388655 : logic lsu_axi_wready_int;
490 903566 : logic lsu_axi_bvalid_int;
491 277 : logic lsu_axi_bready_int;
492 2 : logic [1:0] lsu_axi_bresp_int;
493 394347 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_int;
494 1405087 : logic lsu_axi_arready_int;
495 1083610 : logic lsu_axi_rvalid_int;
496 320256 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_int;
497 105317 : logic [63:0] lsu_axi_rdata_int;
498 2 : logic [1:0] lsu_axi_rresp_int;
499 599433 : logic lsu_axi_rlast_int;
500 :
501 4953803 : logic ifu_axi_awready_ahb;
502 4953803 : logic ifu_axi_wready_ahb;
503 0 : logic ifu_axi_bvalid_ahb;
504 0 : logic ifu_axi_bready_ahb;
505 0 : logic [1:0] ifu_axi_bresp_ahb;
506 5121724 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_ahb;
507 4953803 : logic ifu_axi_arready_ahb;
508 9907574 : logic ifu_axi_rvalid_ahb;
509 5121724 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_ahb;
510 3265312 : logic [63:0] ifu_axi_rdata_ahb;
511 0 : logic [1:0] ifu_axi_rresp_ahb;
512 21 : logic ifu_axi_rlast_ahb;
513 :
514 4953803 : logic ifu_axi_awready_int;
515 4953803 : logic ifu_axi_wready_int;
516 0 : logic ifu_axi_bvalid_int;
517 0 : logic ifu_axi_bready_int;
518 0 : logic [1:0] ifu_axi_bresp_int;
519 5121724 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_int;
520 15867248 : logic ifu_axi_arready_int;
521 20820743 : logic ifu_axi_rvalid_int;
522 9475772 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_int;
523 5657009 : logic [63:0] ifu_axi_rdata_int;
524 2 : logic [1:0] ifu_axi_rresp_int;
525 10913190 : logic ifu_axi_rlast_int;
526 :
527 763 : logic sb_axi_awready_ahb;
528 763 : logic sb_axi_wready_ahb;
529 122 : logic sb_axi_bvalid_ahb;
530 0 : logic sb_axi_bready_ahb;
531 0 : logic [1:0] sb_axi_bresp_ahb;
532 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_bid_ahb;
533 763 : logic sb_axi_arready_ahb;
534 620 : logic sb_axi_rvalid_ahb;
535 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_rid_ahb;
536 682 : logic [63:0] sb_axi_rdata_ahb;
537 0 : logic [1:0] sb_axi_rresp_ahb;
538 21 : logic sb_axi_rlast_ahb;
539 :
540 885 : logic sb_axi_awready_int;
541 885 : logic sb_axi_wready_int;
542 244 : logic sb_axi_bvalid_int;
543 277 : logic sb_axi_bready_int;
544 0 : logic [1:0] sb_axi_bresp_int;
545 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_bid_int;
546 1415 : logic sb_axi_arready_int;
547 1272 : logic sb_axi_rvalid_int;
548 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_rid_int;
549 976 : logic [63:0] sb_axi_rdata_int;
550 0 : logic [1:0] sb_axi_rresp_int;
551 673 : logic sb_axi_rlast_int;
552 :
553 40 : logic dma_axi_awvalid_ahb;
554 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
555 : /*pragma coverage off*/
556 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_ahb;
557 : /*pragma coverage on*/
558 16 : logic [31:0] dma_axi_awaddr_ahb;
559 1 : logic [2:0] dma_axi_awsize_ahb;
560 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
561 : /*pragma coverage off*/
562 : logic [2:0] dma_axi_awprot_ahb;
563 : logic [7:0] dma_axi_awlen_ahb;
564 : logic [1:0] dma_axi_awburst_ahb;
565 : /*pragma coverage on*/
566 40 : logic dma_axi_wvalid_ahb;
567 16 : logic [63:0] dma_axi_wdata_ahb;
568 17 : logic [7:0] dma_axi_wstrb_ahb;
569 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
570 : /*pragma coverage off*/
571 : logic dma_axi_wlast_ahb;
572 : logic dma_axi_bready_ahb;
573 : /*pragma coverage on*/
574 0 : logic dma_axi_arvalid_ahb;
575 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
576 : /*pragma coverage off*/
577 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_ahb;
578 : /*pragma coverage on*/
579 16 : logic [31:0] dma_axi_araddr_ahb;
580 1 : logic [2:0] dma_axi_arsize_ahb;
581 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
582 : /*pragma coverage off*/
583 : logic [2:0] dma_axi_arprot_ahb;
584 : logic [7:0] dma_axi_arlen_ahb;
585 : logic [1:0] dma_axi_arburst_ahb;
586 : logic dma_axi_rready_ahb;
587 : /*pragma coverage on*/
588 :
589 108 : logic dma_axi_awvalid_int;
590 0 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_int;
591 276874 : logic [31:0] dma_axi_awaddr_int;
592 2244 : logic [2:0] dma_axi_awsize_int;
593 276 : logic [2:0] dma_axi_awprot_int;
594 0 : logic [7:0] dma_axi_awlen_int;
595 297 : logic [1:0] dma_axi_awburst_int;
596 108 : logic dma_axi_wvalid_int;
597 119790 : logic [63:0] dma_axi_wdata_int;
598 228164 : logic [7:0] dma_axi_wstrb_int;
599 297 : logic dma_axi_wlast_int;
600 89 : logic dma_axi_bready_int;
601 0 : logic dma_axi_arvalid_int;
602 0 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_int;
603 276874 : logic [31:0] dma_axi_araddr_int;
604 2244 : logic [2:0] dma_axi_arsize_int;
605 276 : logic [2:0] dma_axi_arprot_int;
606 0 : logic [7:0] dma_axi_arlen_int;
607 297 : logic [1:0] dma_axi_arburst_int;
608 21 : logic dma_axi_rready_int;
609 :
610 :
611 : // Icache debug
612 2 : logic [70:0] ifu_ic_debug_rd_data; // diagnostic icache read data
613 20 : logic ifu_ic_debug_rd_data_valid; // diagnostic icache read data valid
614 100 : el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
615 :
616 :
617 7328286 : logic dec_i0_rs1_en_d;
618 3554200 : logic dec_i0_rs2_en_d;
619 5811205 : logic [31:0] gpr_i0_rs1_d;
620 3191893 : logic [31:0] gpr_i0_rs2_d;
621 :
622 2684272 : logic [31:0] dec_i0_result_r;
623 3392829 : logic [31:0] exu_i0_result_x;
624 7003735 : logic [31:1] exu_i0_pc_x;
625 7102308 : logic [31:1] exu_npc_r;
626 :
627 5781366 : el2_alu_pkt_t i0_ap;
628 :
629 : // Trigger signals
630 5 : el2_trigger_pkt_t [3:0] trigger_pkt_any;
631 2 : logic [3:0] lsu_trigger_match_m;
632 :
633 :
634 3690768 : logic [31:0] dec_i0_immed_d;
635 6515524 : logic [12:1] dec_i0_br_immed_d;
636 467136 : logic dec_i0_select_pc_d;
637 :
638 9608797 : logic [31:1] dec_i0_pc_d;
639 1968732 : logic [3:0] dec_i0_rs1_bypass_en_d;
640 205210 : logic [3:0] dec_i0_rs2_bypass_en_d;
641 :
642 6819046 : logic dec_i0_alu_decode_d;
643 5125482 : logic dec_i0_branch_d;
644 :
645 9150159 : logic ifu_miss_state_idle;
646 244 : logic dec_tlu_flush_noredir_r;
647 2 : logic dec_tlu_flush_leak_one_r;
648 20 : logic dec_tlu_flush_err_r;
649 9490858 : logic ifu_i0_valid;
650 10595786 : logic [31:0] ifu_i0_instr;
651 9608797 : logic [31:1] ifu_i0_pc;
652 :
653 3032884 : logic exu_flush_final;
654 :
655 1528430 : logic [31:1] exu_flush_path_final;
656 :
657 2730764 : logic [31:0] exu_lsu_rs1_d;
658 551276 : logic [31:0] exu_lsu_rs2_d;
659 :
660 :
661 8021643 : el2_lsu_pkt_t lsu_p;
662 6775300 : logic dec_qual_lsu_d;
663 :
664 3793779 : logic dec_lsu_valid_raw_d;
665 1270369 : logic [11:0] dec_lsu_offset_d;
666 :
667 488946 : logic [31:0] lsu_result_m;
668 484537 : logic [31:0] lsu_result_corr_r; // This is the ECC corrected data going to RF
669 4 : logic lsu_single_ecc_error_incr; // Increment the ecc counter
670 226981 : el2_lsu_error_pkt_t lsu_error_pkt_r;
671 2 : logic lsu_imprecise_error_load_any;
672 2 : logic lsu_imprecise_error_store_any;
673 740429 : logic [31:0] lsu_imprecise_error_addr_any;
674 269280 : logic lsu_load_stall_any; // This is for blocking loads
675 279584 : logic lsu_store_stall_any; // This is for blocking stores
676 1732990 : logic lsu_idle_any; // doesn't include DMA
677 1732692 : logic lsu_active; // lsu is active. used for clock
678 :
679 :
680 188392 : logic [31:1] lsu_fir_addr; // fast interrupt address
681 0 : logic [1:0] lsu_fir_error; // Error during fast interrupt lookup
682 :
683 : // Non-blocking loads
684 1053002 : logic lsu_nonblock_load_valid_m;
685 1601730 : logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m;
686 0 : logic lsu_nonblock_load_inv_r;
687 1601729 : logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r;
688 1076972 : logic lsu_nonblock_load_data_valid;
689 461122 : logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag;
690 328150 : logic [31:0] lsu_nonblock_load_data;
691 :
692 111994 : logic dec_csr_ren_d;
693 29346657 : logic [31:0] dec_csr_rddata_d;
694 :
695 12560 : logic [31:0] exu_csr_rs1_x;
696 :
697 9314187 : logic dec_tlu_i0_commit_cmt;
698 1281146 : logic dec_tlu_flush_lower_r;
699 1281146 : logic dec_tlu_flush_lower_wb;
700 251412 : logic dec_tlu_i0_kill_writeb_r; // I0 is flushed, don't writeback any results to arch state
701 17362 : logic dec_tlu_fence_i_r; // flush is a fence_i rfnpc, flush icache
702 :
703 281432 : logic [31:1] dec_tlu_flush_path_r;
704 39 : logic [31:0] dec_tlu_mrac_ff; // CSR for memory region control
705 :
706 6533662 : logic ifu_i0_pc4;
707 :
708 209544 : el2_mul_pkt_t mul_p;
709 :
710 864542 : el2_div_pkt_t div_p;
711 2466 : logic dec_div_cancel;
712 :
713 41448 : logic [31:0] exu_div_result;
714 123554 : logic exu_div_wren;
715 :
716 9566855 : logic dec_i0_decode_d;
717 :
718 :
719 5835705 : logic [31:1] pred_correct_npc_x;
720 :
721 5092229 : el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
722 :
723 1735974 : el2_predict_pkt_t exu_mp_pkt;
724 1611034 : logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr;
725 464786 : logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr;
726 1087210 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
727 375994 : logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag;
728 :
729 469426 : logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r;
730 3487456 : logic [1:0] exu_i0_br_hist_r;
731 22483 : logic exu_i0_br_error_r;
732 6778 : logic exu_i0_br_start_error_r;
733 3615482 : logic exu_i0_br_valid_r;
734 1071682 : logic exu_i0_br_mp_r;
735 3222655 : logic exu_i0_br_middle_r;
736 :
737 2448501 : logic exu_i0_br_way_r;
738 :
739 688331 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
740 :
741 0 : logic dma_dccm_req;
742 108 : logic dma_iccm_req;
743 47 : logic [2:0] dma_mem_tag;
744 52 : logic [31:0] dma_mem_addr;
745 33 : logic [2:0] dma_mem_sz;
746 33 : logic dma_mem_write;
747 52 : logic [63:0] dma_mem_wdata;
748 :
749 0 : logic dccm_dma_rvalid;
750 4 : logic dccm_dma_ecc_error;
751 47 : logic [2:0] dccm_dma_rtag;
752 513214 : logic [63:0] dccm_dma_rdata;
753 0 : logic iccm_dma_rvalid;
754 4 : logic iccm_dma_ecc_error;
755 47 : logic [2:0] iccm_dma_rtag;
756 0 : logic [63:0] iccm_dma_rdata;
757 :
758 0 : logic dma_dccm_stall_any; // Stall the ld/st in decode if asserted
759 28 : logic dma_iccm_stall_any; // Stall the fetch
760 3760867 : logic dccm_ready;
761 2998669 : logic iccm_ready;
762 :
763 0 : logic dma_pmu_dccm_read;
764 0 : logic dma_pmu_dccm_write;
765 0 : logic dma_pmu_any_read;
766 108 : logic dma_pmu_any_write;
767 :
768 88 : logic ifu_i0_icaf;
769 128 : logic [1:0] ifu_i0_icaf_type;
770 :
771 :
772 42 : logic ifu_i0_icaf_second;
773 4 : logic ifu_i0_dbecc;
774 0 : logic iccm_dma_sb_error;
775 :
776 9468586 : el2_br_pkt_t i0_brp;
777 8087239 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
778 1127549 : logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
779 656734 : logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
780 :
781 0 : logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
782 0 : logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index
783 :
784 :
785 8702886 : el2_predict_pkt_t dec_i0_predict_p_d;
786 :
787 1127549 : logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d; // DEC predict fghr
788 8087239 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d; // DEC predict index
789 656734 : logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d; // DEC predict branch tag
790 :
791 : // PIC ports
792 8 : logic picm_wren;
793 2 : logic picm_rden;
794 10 : logic picm_mken;
795 2123781 : logic [31:0] picm_rdaddr;
796 2123750 : logic [31:0] picm_wraddr;
797 776110 : logic [31:0] picm_wr_data;
798 6 : logic [31:0] picm_rd_data;
799 :
800 : // feature disable from mfdc
801 0 : logic dec_tlu_external_ldfwd_disable; // disable external load forwarding
802 0 : logic dec_tlu_bpred_disable;
803 9 : logic dec_tlu_wb_coalescing_disable;
804 283 : logic dec_tlu_sideeffect_posted_disable;
805 307 : logic [2:0] dec_tlu_dma_qos_prty; // DMA QoS priority coming from MFDC [18:16]
806 :
807 : // clock gating overrides from mcgc
808 2 : logic dec_tlu_misc_clk_override;
809 2 : logic dec_tlu_ifu_clk_override;
810 2 : logic dec_tlu_lsu_clk_override;
811 2 : logic dec_tlu_bus_clk_override;
812 2 : logic dec_tlu_pic_clk_override;
813 2 : logic dec_tlu_dccm_clk_override;
814 2 : logic dec_tlu_icm_clk_override;
815 :
816 300 : logic dec_tlu_picio_clk_override;
817 :
818 : assign dccm_clk_override = dec_tlu_dccm_clk_override; // dccm memory
819 : assign icm_clk_override = dec_tlu_icm_clk_override; // icache/iccm memory
820 :
821 : // PMP Signals
822 86 : el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES];
823 : logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES];
824 8900699 : logic [31:0] pmp_chan_addr [3];
825 2115916 : el2_pmp_type_pkt_t pmp_chan_type [3];
826 79723 : logic pmp_chan_err [3];
827 :
828 8818296 : logic [31:1] ifu_pmp_addr;
829 44 : logic ifu_pmp_error;
830 2733003 : logic [31:0] lsu_pmp_addr_start;
831 79723 : logic lsu_pmp_error_start;
832 2735183 : logic [31:0] lsu_pmp_addr_end;
833 79723 : logic lsu_pmp_error_end;
834 1312434 : logic lsu_pmp_we;
835 1650450 : logic lsu_pmp_re;
836 :
837 : // -----------------------DEBUG START -------------------------------
838 :
839 1248 : logic [31:0] dbg_cmd_addr; // the address of the debug command to used by the core
840 1410 : logic [31:0] dbg_cmd_wrdata; // If the debug command is a write command, this has the data to be written to the CSR/GPR
841 2690 : logic dbg_cmd_valid; // commad is being driven by the dbg module. One pulse. Only dirven when core_halted has been seen
842 300 : logic dbg_cmd_write; // 1: write command; 0: read_command
843 1536 : logic [1:0] dbg_cmd_type; // 0:gpr 1:csr 2: memory
844 932 : logic [1:0] dbg_cmd_size; // size of the abstract mem access debug command
845 8 : logic dbg_halt_req; // Sticky signal indicating that the debug module wants to start the entering of debug mode ( start the halting sequence )
846 10 : logic dbg_resume_req; // Sticky signal indicating that the debug module wants to resume from debug mode
847 298 : logic dbg_core_rst_l; // Core reset from DM
848 :
849 2690 : logic core_dbg_cmd_done; // Final muxed cmd done to debug
850 4 : logic core_dbg_cmd_fail; // Final muxed cmd done to debug
851 2684272 : logic [31:0] core_dbg_rddata; // Final muxed cmd done to debug
852 :
853 4 : logic dma_dbg_cmd_done; // Abstarct memory command sent to dma is done
854 4 : logic dma_dbg_cmd_fail; // Abstarct memory command sent to dma failed
855 23 : logic [31:0] dma_dbg_rddata; // Read data for abstract memory access
856 :
857 2690 : logic dbg_dma_bubble; // Debug needs a bubble to send a valid
858 2690 : logic dma_dbg_ready; // DMA is ready to accept debug request
859 :
860 2684272 : logic [31:0] dec_dbg_rddata; // The core drives this data ( intercepts the pipe and sends it here )
861 2686 : logic dec_dbg_cmd_done; // This will be treated like a valid signal
862 0 : logic dec_dbg_cmd_fail; // Abstract command failed
863 114 : logic dec_tlu_mpc_halted_only; // Only halted due to MPC
864 126 : logic dec_tlu_dbg_halted; // The core has finished the queiscing sequence. Sticks this signal high
865 10 : logic dec_tlu_resume_ack;
866 124 : logic dec_tlu_debug_mode; // Core is in debug mode
867 528 : logic dec_debug_wdata_rs1_d;
868 0 : logic dec_tlu_force_halt; // halt has been forced
869 :
870 9566853 : logic [1:0] dec_data_en;
871 9376444 : logic [1:0] dec_ctl_en;
872 :
873 : // PMU Signals
874 1071682 : logic exu_pmu_i0_br_misp;
875 3439916 : logic exu_pmu_i0_br_ataken;
876 3522632 : logic exu_pmu_i0_pc4;
877 :
878 1062136 : logic lsu_pmu_load_external_m;
879 815154 : logic lsu_pmu_store_external_m;
880 34506 : logic lsu_pmu_misaligned_m;
881 1879131 : logic lsu_pmu_bus_trxn;
882 25936 : logic lsu_pmu_bus_misaligned;
883 4 : logic lsu_pmu_bus_error;
884 56032 : logic lsu_pmu_bus_busy;
885 :
886 2165083 : logic ifu_pmu_fetch_stall;
887 9410225 : logic ifu_pmu_ic_miss;
888 29197 : logic ifu_pmu_ic_hit;
889 0 : logic ifu_pmu_bus_error;
890 6456771 : logic ifu_pmu_bus_busy;
891 15866964 : logic ifu_pmu_bus_trxn;
892 :
893 414 : logic active_state;
894 115209064 : logic free_clk;
895 115209064 : logic active_clk;
896 2 : logic dec_pause_state_cg;
897 :
898 2 : logic lsu_nonblock_load_data_error;
899 :
900 9085951 : logic [15:0] ifu_i0_cinst;
901 :
902 : // fast interrupt
903 1 : logic [31:2] dec_tlu_meihap;
904 0 : logic dec_extint_stall;
905 :
906 11891014 : el2_trace_pkt_t trace_rv_trace_pkt;
907 :
908 :
909 4 : logic lsu_fastint_stall_any;
910 :
911 0 : logic [7:0] pic_claimid;
912 0 : logic [3:0] pic_pl, dec_tlu_meicurpl, dec_tlu_meipt;
913 0 : logic mexintpend;
914 0 : logic mhwakeup;
915 :
916 112 : logic dma_active;
917 :
918 :
919 2 : logic pause_state;
920 114 : logic halt_state;
921 :
922 4005928 : logic dec_tlu_core_empty;
923 :
924 : assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
925 :
926 : assign halt_state = o_cpu_halt_status & ~(dma_active | lsu_active);
927 :
928 :
929 : assign active_state = (~(halt_state | pause_state) | dec_tlu_flush_lower_r | dec_tlu_flush_lower_wb) | dec_tlu_misc_clk_override;
930 :
931 : rvoclkhdr free_cg2 ( .clk(clk), .en(1'b1), .l1clk(free_l2clk), .* );
932 : rvoclkhdr active_cg2 ( .clk(clk), .en(active_state), .l1clk(active_l2clk), .* );
933 :
934 : // all other clock headers are 1st level
935 : rvoclkhdr free_cg1 ( .clk(free_l2clk), .en(1'b1), .l1clk(free_clk), .* );
936 : rvoclkhdr active_cg1 ( .clk(active_l2clk), .en(1'b1), .l1clk(active_clk), .* );
937 :
938 :
939 : assign core_dbg_cmd_done = dma_dbg_cmd_done | dec_dbg_cmd_done;
940 : assign core_dbg_cmd_fail = dma_dbg_cmd_fail | dec_dbg_cmd_fail;
941 : assign core_dbg_rddata[31:0] = dma_dbg_cmd_done ? dma_dbg_rddata[31:0] : dec_dbg_rddata[31:0];
942 :
943 : el2_dbg #(.pt(pt)) dbg (
944 : .rst_l(core_rst_l),
945 : .clk(free_l2clk),
946 : .clk_override(dec_tlu_misc_clk_override),
947 :
948 : // AXI signals
949 : .sb_axi_awready(sb_axi_awready_int),
950 : .sb_axi_wready(sb_axi_wready_int),
951 : .sb_axi_bvalid(sb_axi_bvalid_int),
952 : .sb_axi_bresp(sb_axi_bresp_int[1:0]),
953 :
954 : .sb_axi_arready(sb_axi_arready_int),
955 : .sb_axi_rvalid(sb_axi_rvalid_int),
956 : .sb_axi_rdata(sb_axi_rdata_int[63:0]),
957 : .sb_axi_rresp(sb_axi_rresp_int[1:0]),
958 : .*
959 : );
960 :
961 : `ifdef RV_ASSERT_ON
962 : assert_fetch_indbghalt: assert #0 (~(ifu.ifc_fetch_req_f & dec.tlu.dbg_tlu_halted_f & ~dec.tlu.dcsr_single_step_running)) else $display("ERROR: Fetching in dBG halt!");
963 : `endif
964 :
965 : // ----------------- DEBUG END -----------------------------
966 :
967 : assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
968 :
969 : `ifdef RV_USER_MODE
970 :
971 : // Operating privilege mode, 0 - machine, 1 - user
972 420 : logic priv_mode;
973 : // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
974 474 : logic priv_mode_eff;
975 : // Next privilege mode
976 420 : logic priv_mode_ns;
977 :
978 4 : el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
979 :
980 : `endif
981 :
982 : // fetch
983 : el2_ifu #(.pt(pt)) ifu (
984 : .clk(active_l2clk),
985 : .rst_l(core_rst_l),
986 : .dec_tlu_flush_err_wb (dec_tlu_flush_err_r ),
987 : .dec_tlu_flush_noredir_wb (dec_tlu_flush_noredir_r ),
988 : .dec_tlu_fence_i_wb (dec_tlu_fence_i_r ),
989 : .dec_tlu_flush_leak_one_wb (dec_tlu_flush_leak_one_r ),
990 : .dec_tlu_flush_lower_wb (dec_tlu_flush_lower_r ),
991 :
992 : // AXI signals
993 : .ifu_axi_arready(ifu_axi_arready_int),
994 : .ifu_axi_rvalid(ifu_axi_rvalid_int),
995 : .ifu_axi_rid(ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0]),
996 : .ifu_axi_rdata(ifu_axi_rdata_int[63:0]),
997 : .ifu_axi_rresp(ifu_axi_rresp_int[1:0]),
998 :
999 : .*
1000 : );
1001 :
1002 :
1003 : assign iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || ifu_iccm_dma_rd_ecc_single_err;
1004 : assign iccm_ecc_double_error = ifu_iccm_rd_ecc_double_err;
1005 :
1006 : el2_dec #(.pt(pt)) dec (
1007 : .clk(active_l2clk),
1008 : .dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),
1009 : .rst_l(core_rst_l),
1010 : .*
1011 : );
1012 :
1013 : el2_exu #(.pt(pt)) exu (
1014 : .clk(active_l2clk),
1015 : .rst_l(core_rst_l),
1016 : .*
1017 : );
1018 :
1019 : el2_lsu #(.pt(pt)) lsu (
1020 : .clk(active_l2clk),
1021 : .rst_l(core_rst_l),
1022 : .clk_override(dec_tlu_lsu_clk_override),
1023 : .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r),
1024 :
1025 : // AXI signals
1026 : .lsu_axi_awready(lsu_axi_awready_int),
1027 : .lsu_axi_wready(lsu_axi_wready_int),
1028 : .lsu_axi_bvalid(lsu_axi_bvalid_int),
1029 : .lsu_axi_bid(lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0]),
1030 : .lsu_axi_bresp(lsu_axi_bresp_int[1:0]),
1031 :
1032 : .lsu_axi_arready(lsu_axi_arready_int),
1033 : .lsu_axi_rvalid(lsu_axi_rvalid_int),
1034 : .lsu_axi_rid(lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0]),
1035 : .lsu_axi_rdata(lsu_axi_rdata_int[63:0]),
1036 : .lsu_axi_rresp(lsu_axi_rresp_int[1:0]),
1037 : .lsu_axi_rlast(lsu_axi_rlast_int),
1038 :
1039 : .*
1040 :
1041 : );
1042 :
1043 : assign dccm_ecc_single_error = lsu_dccm_rd_ecc_single_err;
1044 : assign dccm_ecc_double_error = lsu_dccm_rd_ecc_double_err;
1045 :
1046 : el2_pic_ctrl #(.pt(pt)) pic_ctrl_inst (
1047 : .clk(free_l2clk),
1048 : .clk_override(dec_tlu_pic_clk_override),
1049 : .io_clk_override(dec_tlu_picio_clk_override),
1050 : .picm_mken (picm_mken),
1051 : .extintsrc_req({extintsrc_req[pt.PIC_TOTAL_INT:1],1'b0}),
1052 : .pl(pic_pl[3:0]),
1053 : .claimid(pic_claimid[7:0]),
1054 : .meicurpl(dec_tlu_meicurpl[3:0]),
1055 : .meipt(dec_tlu_meipt[3:0]),
1056 : .rst_l(core_rst_l),
1057 : .*);
1058 :
1059 : el2_dma_ctrl #(.pt(pt)) dma_ctrl (
1060 : .clk(free_l2clk),
1061 : .rst_l(core_rst_l),
1062 : .clk_override(dec_tlu_misc_clk_override),
1063 :
1064 : // AXI signals
1065 : .dma_axi_awvalid(dma_axi_awvalid_int),
1066 : .dma_axi_awid(dma_axi_awid_int[pt.DMA_BUS_TAG-1:0]),
1067 : .dma_axi_awaddr(dma_axi_awaddr_int[31:0]),
1068 : .dma_axi_awsize(dma_axi_awsize_int[2:0]),
1069 : .dma_axi_wvalid(dma_axi_wvalid_int),
1070 : .dma_axi_wdata(dma_axi_wdata_int[63:0]),
1071 : .dma_axi_wstrb(dma_axi_wstrb_int[7:0]),
1072 : .dma_axi_bready(dma_axi_bready_int),
1073 :
1074 : .dma_axi_arvalid(dma_axi_arvalid_int),
1075 : .dma_axi_arid(dma_axi_arid_int[pt.DMA_BUS_TAG-1:0]),
1076 : .dma_axi_araddr(dma_axi_araddr_int[31:0]),
1077 : .dma_axi_arsize(dma_axi_arsize_int[2:0]),
1078 : .dma_axi_rready(dma_axi_rready_int),
1079 :
1080 : .*
1081 : );
1082 :
1083 : assign pmp_chan_addr[0] = {ifu_pmp_addr, 1'b0};
1084 : assign pmp_chan_type[0] = EXEC;
1085 : assign ifu_pmp_error = pmp_chan_err[0];
1086 : assign pmp_chan_addr[1] = lsu_pmp_addr_start;
1087 : assign pmp_chan_type[1] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
1088 : assign lsu_pmp_error_start = pmp_chan_err[1];
1089 : assign pmp_chan_addr[2] = lsu_pmp_addr_end;
1090 : assign pmp_chan_type[2] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
1091 : assign lsu_pmp_error_end = pmp_chan_err[2];
1092 :
1093 : el2_pmp #(
1094 : .PMP_CHANNELS(3),
1095 : .pt(pt)
1096 : ) pmp (
1097 : .clk (active_l2clk),
1098 : .rst_l(core_rst_l),
1099 : .*
1100 : );
1101 :
1102 : if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB
1103 :
1104 : // AXI4 -> AHB Gasket for LSU
1105 : axi4_to_ahb #(.pt(pt),
1106 : .TAG(pt.LSU_BUS_TAG)) lsu_axi4_to_ahb (
1107 :
1108 : .clk(free_l2clk),
1109 : .free_clk(free_clk),
1110 : .rst_l(core_rst_l),
1111 : .clk_override(dec_tlu_bus_clk_override),
1112 : .bus_clk_en(lsu_bus_clk_en),
1113 : .dec_tlu_force_halt(dec_tlu_force_halt),
1114 :
1115 : // AXI Write Channels
1116 : .axi_awvalid(lsu_axi_awvalid),
1117 : .axi_awready(lsu_axi_awready_ahb),
1118 : .axi_awid(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]),
1119 : .axi_awaddr(lsu_axi_awaddr[31:0]),
1120 : .axi_awsize(lsu_axi_awsize[2:0]),
1121 : .axi_awprot(lsu_axi_awprot[2:0]),
1122 :
1123 : .axi_wvalid(lsu_axi_wvalid),
1124 : .axi_wready(lsu_axi_wready_ahb),
1125 : .axi_wdata(lsu_axi_wdata[63:0]),
1126 : .axi_wstrb(lsu_axi_wstrb[7:0]),
1127 : .axi_wlast(lsu_axi_wlast),
1128 :
1129 : .axi_bvalid(lsu_axi_bvalid_ahb),
1130 : .axi_bready(lsu_axi_bready),
1131 : .axi_bresp(lsu_axi_bresp_ahb[1:0]),
1132 : .axi_bid(lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0]),
1133 :
1134 : // AXI Read Channels
1135 : .axi_arvalid(lsu_axi_arvalid),
1136 : .axi_arready(lsu_axi_arready_ahb),
1137 : .axi_arid(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]),
1138 : .axi_araddr(lsu_axi_araddr[31:0]),
1139 : .axi_arsize(lsu_axi_arsize[2:0]),
1140 : .axi_arprot(lsu_axi_arprot[2:0]),
1141 :
1142 : .axi_rvalid(lsu_axi_rvalid_ahb),
1143 : .axi_rready(lsu_axi_rready),
1144 : .axi_rid(lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0]),
1145 : .axi_rdata(lsu_axi_rdata_ahb[63:0]),
1146 : .axi_rresp(lsu_axi_rresp_ahb[1:0]),
1147 : .axi_rlast(lsu_axi_rlast_ahb),
1148 :
1149 : // AHB-LITE signals
1150 : .ahb_haddr(lsu_haddr[31:0]),
1151 : .ahb_hburst(lsu_hburst),
1152 : .ahb_hmastlock(lsu_hmastlock),
1153 : .ahb_hprot(lsu_hprot[3:0]),
1154 : .ahb_hsize(lsu_hsize[2:0]),
1155 : .ahb_htrans(lsu_htrans[1:0]),
1156 : .ahb_hwrite(lsu_hwrite),
1157 : .ahb_hwdata(lsu_hwdata[63:0]),
1158 :
1159 : .ahb_hrdata(lsu_hrdata[63:0]),
1160 : .ahb_hready(lsu_hready),
1161 : .ahb_hresp(lsu_hresp),
1162 :
1163 : .*
1164 : );
1165 :
1166 : axi4_to_ahb #(.pt(pt),
1167 : .TAG(pt.IFU_BUS_TAG)) ifu_axi4_to_ahb (
1168 : .clk(free_l2clk),
1169 : .free_clk(free_clk),
1170 : .rst_l(core_rst_l),
1171 : .clk_override(dec_tlu_bus_clk_override),
1172 : .bus_clk_en(ifu_bus_clk_en),
1173 : .dec_tlu_force_halt(dec_tlu_force_halt),
1174 :
1175 : // AHB-Lite signals
1176 : .ahb_haddr(haddr[31:0]),
1177 : .ahb_hburst(hburst),
1178 : .ahb_hmastlock(hmastlock),
1179 : .ahb_hprot(hprot[3:0]),
1180 : .ahb_hsize(hsize[2:0]),
1181 : .ahb_htrans(htrans[1:0]),
1182 : .ahb_hwrite(hwrite),
1183 : .ahb_hwdata(hwdata_nc[63:0]),
1184 :
1185 : .ahb_hrdata(hrdata[63:0]),
1186 : .ahb_hready(hready),
1187 : .ahb_hresp(hresp),
1188 :
1189 : // AXI Write Channels
1190 : .axi_awvalid(ifu_axi_awvalid),
1191 : .axi_awready(ifu_axi_awready_ahb),
1192 : .axi_awid(ifu_axi_awid[pt.IFU_BUS_TAG-1:0]),
1193 : .axi_awaddr(ifu_axi_awaddr[31:0]),
1194 : .axi_awsize(ifu_axi_awsize[2:0]),
1195 : .axi_awprot(ifu_axi_awprot[2:0]),
1196 :
1197 : .axi_wvalid(ifu_axi_wvalid),
1198 : .axi_wready(ifu_axi_wready_ahb),
1199 : .axi_wdata(ifu_axi_wdata[63:0]),
1200 : .axi_wstrb(ifu_axi_wstrb[7:0]),
1201 : .axi_wlast(ifu_axi_wlast),
1202 :
1203 : .axi_bvalid(ifu_axi_bvalid_ahb),
1204 : .axi_bready(1'b1),
1205 : .axi_bresp(ifu_axi_bresp_ahb[1:0]),
1206 : .axi_bid(ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0]),
1207 :
1208 : // AXI Read Channels
1209 : .axi_arvalid(ifu_axi_arvalid),
1210 : .axi_arready(ifu_axi_arready_ahb),
1211 : .axi_arid(ifu_axi_arid[pt.IFU_BUS_TAG-1:0]),
1212 : .axi_araddr(ifu_axi_araddr[31:0]),
1213 : .axi_arsize(ifu_axi_arsize[2:0]),
1214 : .axi_arprot(ifu_axi_arprot[2:0]),
1215 :
1216 : .axi_rvalid(ifu_axi_rvalid_ahb),
1217 : .axi_rready(ifu_axi_rready),
1218 : .axi_rid(ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0]),
1219 : .axi_rdata(ifu_axi_rdata_ahb[63:0]),
1220 : .axi_rresp(ifu_axi_rresp_ahb[1:0]),
1221 : .axi_rlast(ifu_axi_rlast_ahb),
1222 : .*
1223 : );
1224 :
1225 : // AXI4 -> AHB Gasket for System Bus
1226 : axi4_to_ahb #(.pt(pt),
1227 : .TAG(pt.SB_BUS_TAG)) sb_axi4_to_ahb (
1228 : .clk(free_l2clk),
1229 : .free_clk(free_clk),
1230 : .rst_l(dbg_rst_l),
1231 : .clk_override(dec_tlu_bus_clk_override),
1232 : .bus_clk_en(dbg_bus_clk_en),
1233 : .dec_tlu_force_halt(1'b0),
1234 :
1235 : // AXI Write Channels
1236 : .axi_awvalid(sb_axi_awvalid),
1237 : .axi_awready(sb_axi_awready_ahb),
1238 : .axi_awid(sb_axi_awid[pt.SB_BUS_TAG-1:0]),
1239 : .axi_awaddr(sb_axi_awaddr[31:0]),
1240 : .axi_awsize(sb_axi_awsize[2:0]),
1241 : .axi_awprot(sb_axi_awprot[2:0]),
1242 :
1243 : .axi_wvalid(sb_axi_wvalid),
1244 : .axi_wready(sb_axi_wready_ahb),
1245 : .axi_wdata(sb_axi_wdata[63:0]),
1246 : .axi_wstrb(sb_axi_wstrb[7:0]),
1247 : .axi_wlast(sb_axi_wlast),
1248 :
1249 : .axi_bvalid(sb_axi_bvalid_ahb),
1250 : .axi_bready(sb_axi_bready),
1251 : .axi_bresp(sb_axi_bresp_ahb[1:0]),
1252 : .axi_bid(sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0]),
1253 :
1254 : // AXI Read Channels
1255 : .axi_arvalid(sb_axi_arvalid),
1256 : .axi_arready(sb_axi_arready_ahb),
1257 : .axi_arid(sb_axi_arid[pt.SB_BUS_TAG-1:0]),
1258 : .axi_araddr(sb_axi_araddr[31:0]),
1259 : .axi_arsize(sb_axi_arsize[2:0]),
1260 : .axi_arprot(sb_axi_arprot[2:0]),
1261 :
1262 : .axi_rvalid(sb_axi_rvalid_ahb),
1263 : .axi_rready(sb_axi_rready),
1264 : .axi_rid(sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0]),
1265 : .axi_rdata(sb_axi_rdata_ahb[63:0]),
1266 : .axi_rresp(sb_axi_rresp_ahb[1:0]),
1267 : .axi_rlast(sb_axi_rlast_ahb),
1268 : // AHB-LITE signals
1269 : .ahb_haddr(sb_haddr[31:0]),
1270 : .ahb_hburst(sb_hburst),
1271 : .ahb_hmastlock(sb_hmastlock),
1272 : .ahb_hprot(sb_hprot[3:0]),
1273 : .ahb_hsize(sb_hsize[2:0]),
1274 : .ahb_htrans(sb_htrans[1:0]),
1275 : .ahb_hwrite(sb_hwrite),
1276 : .ahb_hwdata(sb_hwdata[63:0]),
1277 :
1278 : .ahb_hrdata(sb_hrdata[63:0]),
1279 : .ahb_hready(sb_hready),
1280 : .ahb_hresp(sb_hresp),
1281 :
1282 : .*
1283 : );
1284 :
1285 : //AHB -> AXI4 Gasket for DMA
1286 : ahb_to_axi4 #(.pt(pt),
1287 : .TAG(pt.DMA_BUS_TAG)) dma_ahb_to_axi4 (
1288 : .clk(free_l2clk),
1289 : .rst_l(core_rst_l),
1290 : .clk_override(dec_tlu_bus_clk_override),
1291 : .bus_clk_en(dma_bus_clk_en),
1292 :
1293 : // AXI Write Channels
1294 : .axi_awvalid(dma_axi_awvalid_ahb),
1295 : .axi_awready(dma_axi_awready),
1296 : .axi_awid(dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0]),
1297 : .axi_awaddr(dma_axi_awaddr_ahb[31:0]),
1298 : .axi_awsize(dma_axi_awsize_ahb[2:0]),
1299 : .axi_awprot(dma_axi_awprot_ahb[2:0]),
1300 : .axi_awlen(dma_axi_awlen_ahb[7:0]),
1301 : .axi_awburst(dma_axi_awburst_ahb[1:0]),
1302 :
1303 : .axi_wvalid(dma_axi_wvalid_ahb),
1304 : .axi_wready(dma_axi_wready),
1305 : .axi_wdata(dma_axi_wdata_ahb[63:0]),
1306 : .axi_wstrb(dma_axi_wstrb_ahb[7:0]),
1307 : .axi_wlast(dma_axi_wlast_ahb),
1308 :
1309 : .axi_bvalid(dma_axi_bvalid),
1310 : .axi_bready(dma_axi_bready_ahb),
1311 : .axi_bresp(dma_axi_bresp[1:0]),
1312 : .axi_bid(dma_axi_bid[pt.DMA_BUS_TAG-1:0]),
1313 :
1314 : // AXI Read Channels
1315 : .axi_arvalid(dma_axi_arvalid_ahb),
1316 : .axi_arready(dma_axi_arready),
1317 : .axi_arid(dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0]),
1318 : .axi_araddr(dma_axi_araddr_ahb[31:0]),
1319 : .axi_arsize(dma_axi_arsize_ahb[2:0]),
1320 : .axi_arprot(dma_axi_arprot_ahb[2:0]),
1321 : .axi_arlen(dma_axi_arlen_ahb[7:0]),
1322 : .axi_arburst(dma_axi_arburst_ahb[1:0]),
1323 :
1324 : .axi_rvalid(dma_axi_rvalid),
1325 : .axi_rready(dma_axi_rready_ahb),
1326 : .axi_rid(dma_axi_rid[pt.DMA_BUS_TAG-1:0]),
1327 : .axi_rdata(dma_axi_rdata[63:0]),
1328 : .axi_rresp(dma_axi_rresp[1:0]),
1329 :
1330 : // AHB signals
1331 : .ahb_haddr(dma_haddr[31:0]),
1332 : .ahb_hburst(dma_hburst),
1333 : .ahb_hmastlock(dma_hmastlock),
1334 : .ahb_hprot(dma_hprot[3:0]),
1335 : .ahb_hsize(dma_hsize[2:0]),
1336 : .ahb_htrans(dma_htrans[1:0]),
1337 : .ahb_hwrite(dma_hwrite),
1338 : .ahb_hwdata(dma_hwdata[63:0]),
1339 :
1340 : .ahb_hrdata(dma_hrdata[63:0]),
1341 : .ahb_hreadyout(dma_hreadyout),
1342 : .ahb_hresp(dma_hresp),
1343 : .ahb_hreadyin(dma_hreadyin),
1344 : .ahb_hsel(dma_hsel),
1345 : .*
1346 : );
1347 :
1348 : end
1349 :
1350 : // Drive the final AXI inputs
1351 : assign lsu_axi_awready_int = pt.BUILD_AHB_LITE ? lsu_axi_awready_ahb : lsu_axi_awready;
1352 : assign lsu_axi_wready_int = pt.BUILD_AHB_LITE ? lsu_axi_wready_ahb : lsu_axi_wready;
1353 : assign lsu_axi_bvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_bvalid_ahb : lsu_axi_bvalid;
1354 : assign lsu_axi_bready_int = pt.BUILD_AHB_LITE ? lsu_axi_bready_ahb : lsu_axi_bready;
1355 : assign lsu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bresp_ahb[1:0] : lsu_axi_bresp[1:0];
1356 : assign lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_bid[pt.LSU_BUS_TAG-1:0];
1357 : assign lsu_axi_arready_int = pt.BUILD_AHB_LITE ? lsu_axi_arready_ahb : lsu_axi_arready;
1358 : assign lsu_axi_rvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_rvalid_ahb : lsu_axi_rvalid;
1359 : assign lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_rid[pt.LSU_BUS_TAG-1:0];
1360 : assign lsu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? lsu_axi_rdata_ahb[63:0] : lsu_axi_rdata[63:0];
1361 : assign lsu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rresp_ahb[1:0] : lsu_axi_rresp[1:0];
1362 : assign lsu_axi_rlast_int = pt.BUILD_AHB_LITE ? lsu_axi_rlast_ahb : lsu_axi_rlast;
1363 :
1364 : assign ifu_axi_awready_int = pt.BUILD_AHB_LITE ? ifu_axi_awready_ahb : ifu_axi_awready;
1365 : assign ifu_axi_wready_int = pt.BUILD_AHB_LITE ? ifu_axi_wready_ahb : ifu_axi_wready;
1366 : assign ifu_axi_bvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_bvalid_ahb : ifu_axi_bvalid;
1367 : assign ifu_axi_bready_int = pt.BUILD_AHB_LITE ? ifu_axi_bready_ahb : ifu_axi_bready;
1368 : assign ifu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bresp_ahb[1:0] : ifu_axi_bresp[1:0];
1369 : assign ifu_axi_bid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_bid[pt.IFU_BUS_TAG-1:0];
1370 : assign ifu_axi_arready_int = pt.BUILD_AHB_LITE ? ifu_axi_arready_ahb : ifu_axi_arready;
1371 : assign ifu_axi_rvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_rvalid_ahb : ifu_axi_rvalid;
1372 : assign ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_rid[pt.IFU_BUS_TAG-1:0];
1373 : assign ifu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? ifu_axi_rdata_ahb[63:0] : ifu_axi_rdata[63:0];
1374 : assign ifu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rresp_ahb[1:0] : ifu_axi_rresp[1:0];
1375 : assign ifu_axi_rlast_int = pt.BUILD_AHB_LITE ? ifu_axi_rlast_ahb : ifu_axi_rlast;
1376 :
1377 : assign sb_axi_awready_int = pt.BUILD_AHB_LITE ? sb_axi_awready_ahb : sb_axi_awready;
1378 : assign sb_axi_wready_int = pt.BUILD_AHB_LITE ? sb_axi_wready_ahb : sb_axi_wready;
1379 : assign sb_axi_bvalid_int = pt.BUILD_AHB_LITE ? sb_axi_bvalid_ahb : sb_axi_bvalid;
1380 : assign sb_axi_bready_int = pt.BUILD_AHB_LITE ? sb_axi_bready_ahb : sb_axi_bready;
1381 : assign sb_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_bresp_ahb[1:0] : sb_axi_bresp[1:0];
1382 : assign sb_axi_bid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_bid[pt.SB_BUS_TAG-1:0];
1383 : assign sb_axi_arready_int = pt.BUILD_AHB_LITE ? sb_axi_arready_ahb : sb_axi_arready;
1384 : assign sb_axi_rvalid_int = pt.BUILD_AHB_LITE ? sb_axi_rvalid_ahb : sb_axi_rvalid;
1385 : assign sb_axi_rid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_rid[pt.SB_BUS_TAG-1:0];
1386 : assign sb_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? sb_axi_rdata_ahb[63:0] : sb_axi_rdata[63:0];
1387 : assign sb_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_rresp_ahb[1:0] : sb_axi_rresp[1:0];
1388 : assign sb_axi_rlast_int = pt.BUILD_AHB_LITE ? sb_axi_rlast_ahb : sb_axi_rlast;
1389 :
1390 : assign dma_axi_awvalid_int = pt.BUILD_AHB_LITE ? dma_axi_awvalid_ahb : dma_axi_awvalid;
1391 : assign dma_axi_awid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_awid[pt.DMA_BUS_TAG-1:0];
1392 : assign dma_axi_awaddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_awaddr_ahb[31:0] : dma_axi_awaddr[31:0];
1393 : assign dma_axi_awsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awsize_ahb[2:0] : dma_axi_awsize[2:0];
1394 : assign dma_axi_awprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awprot_ahb[2:0] : dma_axi_awprot[2:0];
1395 : assign dma_axi_awlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_awlen_ahb[7:0] : dma_axi_awlen[7:0];
1396 : assign dma_axi_awburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_awburst_ahb[1:0] : dma_axi_awburst[1:0];
1397 : assign dma_axi_wvalid_int = pt.BUILD_AHB_LITE ? dma_axi_wvalid_ahb : dma_axi_wvalid;
1398 : assign dma_axi_wdata_int[63:0] = pt.BUILD_AHB_LITE ? dma_axi_wdata_ahb[63:0] : dma_axi_wdata;
1399 : assign dma_axi_wstrb_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_wstrb_ahb[7:0] : dma_axi_wstrb[7:0];
1400 : assign dma_axi_wlast_int = pt.BUILD_AHB_LITE ? dma_axi_wlast_ahb : dma_axi_wlast;
1401 : assign dma_axi_bready_int = pt.BUILD_AHB_LITE ? dma_axi_bready_ahb : dma_axi_bready;
1402 : assign dma_axi_arvalid_int = pt.BUILD_AHB_LITE ? dma_axi_arvalid_ahb : dma_axi_arvalid;
1403 : assign dma_axi_arid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_arid[pt.DMA_BUS_TAG-1:0];
1404 : assign dma_axi_araddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_araddr_ahb[31:0] : dma_axi_araddr[31:0];
1405 : assign dma_axi_arsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arsize_ahb[2:0] : dma_axi_arsize[2:0];
1406 : assign dma_axi_arprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arprot_ahb[2:0] : dma_axi_arprot[2:0];
1407 : assign dma_axi_arlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_arlen_ahb[7:0] : dma_axi_arlen[7:0];
1408 : assign dma_axi_arburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_arburst_ahb[1:0] : dma_axi_arburst[1:0];
1409 : assign dma_axi_rready_int = pt.BUILD_AHB_LITE ? dma_axi_rready_ahb : dma_axi_rready;
1410 :
1411 :
1412 : if (pt.BUILD_AHB_LITE == 1) begin
1413 : `ifdef RV_ASSERT_ON
1414 : property ahb_trxn_aligned;
1415 : @(posedge clk) disable iff(~rst_l) (lsu_htrans[1:0] != 2'b0) |-> ((lsu_hsize[2:0] == 3'h0) |
1416 : ((lsu_hsize[2:0] == 3'h1) & (lsu_haddr[0] == 1'b0)) |
1417 : ((lsu_hsize[2:0] == 3'h2) & (lsu_haddr[1:0] == 2'b0)) |
1418 : ((lsu_hsize[2:0] == 3'h3) & (lsu_haddr[2:0] == 3'b0)));
1419 : endproperty
1420 : assert_ahb_trxn_aligned: assert property (ahb_trxn_aligned) else
1421 : $display("Assertion ahb_trxn_aligned failed: lsu_htrans=2'h%h, lsu_hsize=3'h%h, lsu_haddr=32'h%h",lsu_htrans[1:0], lsu_hsize[2:0], lsu_haddr[31:0]);
1422 :
1423 : property dma_trxn_aligned;
1424 : @(posedge clk) disable iff(~rst_l) (dma_htrans[1:0] != 2'b0) |-> ((dma_hsize[2:0] == 3'h0) |
1425 : ((dma_hsize[2:0] == 3'h1) & (dma_haddr[0] == 1'b0)) |
1426 : ((dma_hsize[2:0] == 3'h2) & (dma_haddr[1:0] == 2'b0)) |
1427 : ((dma_hsize[2:0] == 3'h3) & (dma_haddr[2:0] == 3'b0)));
1428 : endproperty
1429 :
1430 :
1431 : `endif
1432 : end // if (pt.BUILD_AHB_LITE == 1)
1433 :
1434 :
1435 : // unpack packet
1436 : // also need retires_p==3
1437 :
1438 : assign trace_rv_i_insn_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_insn_ip[31:0];
1439 :
1440 : assign trace_rv_i_address_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_address_ip[31:0];
1441 :
1442 : assign trace_rv_i_valid_ip = trace_rv_trace_pkt.trace_rv_i_valid_ip;
1443 :
1444 : assign trace_rv_i_exception_ip = trace_rv_trace_pkt.trace_rv_i_exception_ip;
1445 :
1446 : assign trace_rv_i_ecause_ip[4:0] = trace_rv_trace_pkt.trace_rv_i_ecause_ip[4:0];
1447 :
1448 : assign trace_rv_i_interrupt_ip = trace_rv_trace_pkt.trace_rv_i_interrupt_ip;
1449 :
1450 : assign trace_rv_i_tval_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_tval_ip[31:0];
1451 :
1452 :
1453 :
1454 : endmodule // el2_veer
1455 :
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