Coverage dashboard¶ Summary reports (all tests)¶ all coverage Individual test reports¶ ahb_bitmanip ahb_cmark ahb_cmark_dccm ahb_cmark_iccm ahb_csr_access ahb_csr_misa ahb_csr_mseccfg ahb_csr_mstatus ahb_dhry ahb_ecc ahb_hello_world ahb_hello_world_dccm ahb_icache ahb_insns ahb_irq ahb_modesw ahb_perf_counters ahb_pmp ahb_write_unaligned axi_bitmanip axi_clk_override axi_cmark axi_cmark_dccm axi_cmark_iccm axi_core_pause axi_csr_access axi_csr_misa axi_csr_mseccfg axi_csr_mstatus axi_dbus_nonblocking_load_error axi_dbus_store_error axi_dhry axi_dside_access_across_region_boundary axi_dside_access_region_prediction_error axi_dside_core_local_access_unmapped_address_error axi_dside_pic_access_error axi_dside_size_misaligned_access_to_non_idempotent_address axi_ebreak_ecall axi_ecc axi_hello_world axi_hello_world_dccm axi_hello_world_iccm axi_icache axi_illegal_instruction axi_insns axi_internal_timer_ints axi_irq axi_iside_core_local_unmapped_address_error axi_iside_fetch_precise_bus_error axi_lsu_trigger_hit axi_machine_external_ints axi_machine_external_vec_ints axi_modesw axi_nmi_pin_assertion axi_perf_counters axi_pmp axi_write_unaligned dccm_test_readwrite dec_ib_test_dec_ib dec_tl_test_dec_tl dma_test_address dma_test_debug_address dma_test_debug_read dma_test_debug_write dma_test_ecc dma_test_read dma_test_reset dma_test_write dmi_test_dmi_read_write dmi_test_jtag_ir exu_alu_test_arith exu_alu_test_logic exu_alu_test_zba exu_alu_test_zbb exu_alu_test_zbp exu_alu_test_zbs exu_div_test_div exu_mul_test_mul iccm_test_readwrite ifu_compress_test_compress lib_ahb_to_axi4_test_read lib_ahb_to_axi4_test_write lib_axi4_to_ahb_test_axi lib_axi4_to_ahb_test_axi_read_channel lib_axi4_to_ahb_test_axi_read_channel_multiple lib_axi4_to_ahb_test_axi_write_channel lsu_tl_test_lsu_tl openocd_ahb_lite openocd_axi4 openocd_gdb_test_ahb_lite openocd_gdb_test_axi4 pic_gw_test_gateway pic_test_clken pic_test_config pic_test_prioritization pic_test_reset pic_test_servicing pmp_test_address_matching pmp_test_multiple_configs pmp_test_xwr_access riscof_ riscof_u riscv-dv__riscv_arithmetic_basic_test riscv-dv__riscv_bitmanip_balanced_test_veer riscv-dv__riscv_bitmanip_full_test_veer riscv-dv__riscv_ebreak_debug_mode_test riscv-dv__riscv_ebreak_test riscv-dv__riscv_full_interrupt_test riscv-dv__riscv_hint_instr_test riscv-dv__riscv_illegal_instr_test riscv-dv__riscv_jump_stress_test riscv-dv__riscv_loop_test riscv-dv__riscv_mmu_stress_test riscv-dv__riscv_no_fence_test riscv-dv__riscv_non_compressed_instr_test riscv-dv__riscv_pmp_disable_all_regions_test_veer riscv-dv__riscv_pmp_full_random_test_veer riscv-dv__riscv_pmp_out_of_bounds_test_veer riscv-dv__riscv_pmp_region_exec_test_veer riscv-dv__riscv_pmp_test riscv-dv__riscv_rand_instr_test riscv-dv__riscv_rand_jump_test riscv-dv__riscv_unaligned_load_store_test riscv-dv__riscv_user_mode_rand_test riscv-dv_u_riscv_arithmetic_basic_test riscv-dv_u_riscv_bitmanip_balanced_test_veer riscv-dv_u_riscv_bitmanip_full_test_veer riscv-dv_u_riscv_ebreak_debug_mode_test riscv-dv_u_riscv_ebreak_test riscv-dv_u_riscv_full_interrupt_test riscv-dv_u_riscv_hint_instr_test riscv-dv_u_riscv_illegal_instr_test riscv-dv_u_riscv_jump_stress_test riscv-dv_u_riscv_loop_test riscv-dv_u_riscv_mmu_stress_test riscv-dv_u_riscv_no_fence_test riscv-dv_u_riscv_non_compressed_instr_test riscv-dv_u_riscv_pmp_disable_all_regions_test_veer riscv-dv_u_riscv_pmp_full_random_test_veer riscv-dv_u_riscv_pmp_out_of_bounds_test_veer riscv-dv_u_riscv_pmp_region_exec_test_veer riscv-dv_u_riscv_pmp_test riscv-dv_u_riscv_rand_instr_test riscv-dv_u_riscv_rand_jump_test riscv-dv_u_riscv_unaligned_load_store_test riscv-dv_u_riscv_user_mode_rand_test test_pyuvm Last update: 2025-01-08