Coverage dashboard¶ Summary reports (all tests)¶ all coverage Individual test reports¶ ahb_cmark ahb_cmark_dccm ahb_cmark_iccm ahb_csr_access ahb_csr_misa ahb_csr_mseccfg ahb_csr_mstatus ahb_dhry ahb_ecc ahb_hello_world ahb_hello_world_dccm ahb_hello_world_iccm ahb_insns ahb_irq ahb_modesw ahb_perf_counters ahb_pmp ahb_write_unaligned axi_clk_override axi_cmark axi_cmark_dccm axi_cmark_iccm axi_core_pause axi_csr_access axi_csr_misa axi_csr_mseccfg axi_csr_mstatus axi_dbus_nonblocking_load_error axi_dbus_store_error axi_dhry axi_dside_access_across_region_boundary axi_dside_access_region_prediction_error axi_dside_core_local_access_unmapped_address_error axi_dside_pic_access_error axi_dside_size_misaligned_access_to_non_idempotent_address axi_ebreak_ecall axi_ecc axi_hello_world axi_hello_world_dccm axi_hello_world_iccm axi_illegal_instruction axi_insns axi_internal_timer_ints axi_irq axi_iside_core_local_unmapped_address_error axi_iside_fetch_precise_bus_error axi_lsu_trigger_hit axi_machine_external_ints axi_machine_external_vec_ints axi_modesw axi_nmi_pin_assertion axi_perf_counters axi_pmp axi_write_unaligned dccm_test_readwrite_default dccm_test_readwrite_default_ahb dccm_test_readwrite_high_perf dccm_test_readwrite_typical_pd dec_ib_test_dec_ib_default dec_ib_test_dec_ib_default_ahb dec_ib_test_dec_ib_high_perf dec_ib_test_dec_ib_typical_pd dec_tl_test_dec_tl_default dec_tl_test_dec_tl_default_ahb dec_tl_test_dec_tl_high_perf dec_tl_test_dec_tl_typical_pd dma_test_address_default dma_test_address_default_ahb dma_test_address_high_perf dma_test_address_typical_pd dma_test_debug_address_default dma_test_debug_address_default_ahb dma_test_debug_address_high_perf dma_test_debug_address_typical_pd dma_test_debug_read_default dma_test_debug_read_default_ahb dma_test_debug_read_high_perf dma_test_debug_read_typical_pd dma_test_debug_write_default dma_test_debug_write_default_ahb dma_test_debug_write_high_perf dma_test_debug_write_typical_pd dma_test_ecc_default dma_test_ecc_default_ahb dma_test_ecc_high_perf dma_test_ecc_typical_pd dma_test_read_default dma_test_read_default_ahb dma_test_read_high_perf dma_test_read_typical_pd dma_test_reset_default dma_test_reset_default_ahb dma_test_reset_high_perf dma_test_reset_typical_pd dma_test_write_default dma_test_write_default_ahb dma_test_write_high_perf dma_test_write_typical_pd dmi_test_dmi_read_write_default dmi_test_dmi_read_write_default_ahb dmi_test_dmi_read_write_high_perf dmi_test_dmi_read_write_typical_pd dmi_test_jtag_ir_default dmi_test_jtag_ir_default_ahb dmi_test_jtag_ir_high_perf dmi_test_jtag_ir_typical_pd exu_alu_test_arith_default exu_alu_test_arith_default_ahb exu_alu_test_arith_high_perf exu_alu_test_arith_typical_pd exu_alu_test_logic_default exu_alu_test_logic_default_ahb exu_alu_test_logic_high_perf exu_alu_test_logic_typical_pd exu_alu_test_zba_default exu_alu_test_zba_default_ahb exu_alu_test_zba_high_perf exu_alu_test_zba_typical_pd exu_alu_test_zbb_default exu_alu_test_zbb_default_ahb exu_alu_test_zbb_high_perf exu_alu_test_zbb_typical_pd exu_alu_test_zbp_default exu_alu_test_zbp_default_ahb exu_alu_test_zbp_high_perf exu_alu_test_zbp_typical_pd exu_alu_test_zbs_default exu_alu_test_zbs_default_ahb exu_alu_test_zbs_high_perf exu_alu_test_zbs_typical_pd exu_div_test_div_default exu_div_test_div_default_ahb exu_div_test_div_high_perf exu_div_test_div_typical_pd exu_mul_test_mul_default exu_mul_test_mul_default_ahb exu_mul_test_mul_high_perf exu_mul_test_mul_typical_pd iccm_test_readwrite_default iccm_test_readwrite_default_ahb iccm_test_readwrite_high_perf iccm_test_readwrite_typical_pd ifu_compress_test_compress_default ifu_compress_test_compress_default_ahb ifu_compress_test_compress_high_perf ifu_compress_test_compress_typical_pd lib_ahb_to_axi4_test_read_default lib_ahb_to_axi4_test_read_default_ahb lib_ahb_to_axi4_test_read_high_perf lib_ahb_to_axi4_test_read_typical_pd lib_ahb_to_axi4_test_write_default lib_ahb_to_axi4_test_write_default_ahb lib_ahb_to_axi4_test_write_high_perf lib_ahb_to_axi4_test_write_typical_pd lib_axi4_to_ahb_test_axi_default lib_axi4_to_ahb_test_axi_default_ahb lib_axi4_to_ahb_test_axi_high_perf lib_axi4_to_ahb_test_axi_read_channel_default lib_axi4_to_ahb_test_axi_read_channel_default_ahb lib_axi4_to_ahb_test_axi_read_channel_high_perf lib_axi4_to_ahb_test_axi_read_channel_typical_pd lib_axi4_to_ahb_test_axi_typical_pd lib_axi4_to_ahb_test_axi_write_channel_default lib_axi4_to_ahb_test_axi_write_channel_default_ahb lib_axi4_to_ahb_test_axi_write_channel_high_perf lib_axi4_to_ahb_test_axi_write_channel_typical_pd lsu_tl_test_lsu_tl_default lsu_tl_test_lsu_tl_default_ahb lsu_tl_test_lsu_tl_high_perf lsu_tl_test_lsu_tl_typical_pd openocd_ahb_lite openocd_axi4 openocd_gdb_test_ahb_lite openocd_gdb_test_axi4 pic_gw_test_gateway_default pic_gw_test_gateway_default_ahb pic_gw_test_gateway_high_perf pic_gw_test_gateway_typical_pd pic_test_clken_default pic_test_clken_default_ahb pic_test_clken_high_perf pic_test_clken_typical_pd pic_test_config_default pic_test_config_default_ahb pic_test_config_high_perf pic_test_config_typical_pd pic_test_prioritization_default pic_test_prioritization_default_ahb pic_test_prioritization_high_perf pic_test_prioritization_typical_pd pic_test_reset_default pic_test_reset_default_ahb pic_test_reset_high_perf pic_test_reset_typical_pd pic_test_servicing_default pic_test_servicing_default_ahb pic_test_servicing_high_perf pic_test_servicing_typical_pd pmp_test_address_matching_default pmp_test_address_matching_default_ahb pmp_test_address_matching_high_perf pmp_test_address_matching_typical_pd pmp_test_multiple_configs_default pmp_test_multiple_configs_default_ahb pmp_test_multiple_configs_high_perf pmp_test_multiple_configs_typical_pd pmp_test_xwr_access_default pmp_test_xwr_access_default_ahb pmp_test_xwr_access_high_perf pmp_test_xwr_access_typical_pd riscof_ riscof_u riscv-dv__riscv_arithmetic_basic_test riscv-dv__riscv_bitmanip_balanced_test_veer riscv-dv__riscv_bitmanip_full_test_veer riscv-dv__riscv_ebreak_debug_mode_test riscv-dv__riscv_ebreak_test riscv-dv__riscv_full_interrupt_test riscv-dv__riscv_hint_instr_test riscv-dv__riscv_illegal_instr_test riscv-dv__riscv_jump_stress_test riscv-dv__riscv_loop_test riscv-dv__riscv_mmu_stress_test riscv-dv__riscv_no_fence_test riscv-dv__riscv_non_compressed_instr_test riscv-dv__riscv_pmp_disable_all_regions_test_veer riscv-dv__riscv_pmp_full_random_test_veer riscv-dv__riscv_pmp_out_of_bounds_test_veer riscv-dv__riscv_pmp_region_exec_test_veer riscv-dv__riscv_pmp_test riscv-dv__riscv_rand_instr_test riscv-dv__riscv_rand_jump_test riscv-dv__riscv_unaligned_load_store_test riscv-dv__riscv_user_mode_rand_test riscv-dv_u_riscv_arithmetic_basic_test riscv-dv_u_riscv_bitmanip_balanced_test_veer riscv-dv_u_riscv_bitmanip_full_test_veer riscv-dv_u_riscv_ebreak_debug_mode_test riscv-dv_u_riscv_ebreak_test riscv-dv_u_riscv_full_interrupt_test riscv-dv_u_riscv_hint_instr_test riscv-dv_u_riscv_illegal_instr_test riscv-dv_u_riscv_jump_stress_test riscv-dv_u_riscv_loop_test riscv-dv_u_riscv_mmu_stress_test riscv-dv_u_riscv_no_fence_test riscv-dv_u_riscv_non_compressed_instr_test riscv-dv_u_riscv_pmp_disable_all_regions_test_veer riscv-dv_u_riscv_pmp_full_random_test_veer riscv-dv_u_riscv_pmp_out_of_bounds_test_veer riscv-dv_u_riscv_pmp_region_exec_test_veer riscv-dv_u_riscv_pmp_test riscv-dv_u_riscv_rand_instr_test riscv-dv_u_riscv_rand_jump_test riscv-dv_u_riscv_unaligned_load_store_test riscv-dv_u_riscv_user_mode_rand_test test_pyuvm Last update: 2024-11-25