Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : // Copyright (c) 2023 Antmicro <www.antmicro.com>
4 : //
5 : // Licensed under the Apache License, Version 2.0 (the "License");
6 : // you may not use this file except in compliance with the License.
7 : // You may obtain a copy of the License at
8 : //
9 : // http://www.apache.org/licenses/LICENSE-2.0
10 : //
11 : // Unless required by applicable law or agreed to in writing, software
12 : // distributed under the License is distributed on an "AS IS" BASIS,
13 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 : // See the License for the specific language governing permissions and
15 : // limitations under the License.
16 :
17 : //********************************************************************************
18 : // $Id$
19 : //
20 : // Function: Top wrapper file with el2_veer/mem instantiated inside
21 : // Comments:
22 : //
23 : //********************************************************************************
24 : module el2_veer_wrapper
25 : import el2_pkg::*;
26 : #(
27 : `include "el2_param.vh"
28 : )
29 : (
30 69887189 : input logic clk,
31 338 : input logic rst_l,
32 338 : input logic dbg_rst_l,
33 0 : input logic [31:1] rst_vec,
34 3 : input logic nmi_int,
35 16 : input logic [31:1] nmi_vec,
36 0 : input logic [31:1] jtag_id,
37 :
38 :
39 579463 : output logic [31:0] trace_rv_i_insn_ip,
40 340 : output logic [31:0] trace_rv_i_address_ip,
41 6173412 : output logic trace_rv_i_valid_ip,
42 5208 : output logic trace_rv_i_exception_ip,
43 4 : output logic [4:0] trace_rv_i_ecause_ip,
44 28 : output logic trace_rv_i_interrupt_ip,
45 62 : output logic [31:0] trace_rv_i_tval_ip,
46 :
47 : // Bus signals
48 : `ifdef RV_BUILD_AXI4
49 : //-------------------------- LSU AXI signals--------------------------
50 : // AXI Write Channels
51 659926 : output logic lsu_axi_awvalid,
52 669548 : input logic lsu_axi_awready,
53 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
54 282 : output logic [31:0] lsu_axi_awaddr,
55 318 : output logic [3:0] lsu_axi_awregion,
56 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
57 : /*verilator coverage_off*/
58 : output logic [7:0] lsu_axi_awlen,
59 : /*verilator coverage_on*/
60 0 : output logic [2:0] lsu_axi_awsize,
61 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
62 : /*verilator coverage_off*/
63 : output logic [1:0] lsu_axi_awburst,
64 : output logic lsu_axi_awlock,
65 : /*verilator coverage_on*/
66 1773 : output logic [3:0] lsu_axi_awcache,
67 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
68 : /*verilator coverage_off*/
69 : output logic [2:0] lsu_axi_awprot,
70 : output logic [3:0] lsu_axi_awqos,
71 : /*verilator coverage_on*/
72 :
73 659926 : output logic lsu_axi_wvalid,
74 669548 : input logic lsu_axi_wready,
75 29795 : output logic [63:0] lsu_axi_wdata,
76 185761 : output logic [7:0] lsu_axi_wstrb,
77 319 : output logic lsu_axi_wlast,
78 :
79 669290 : input logic lsu_axi_bvalid,
80 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
81 : /*verilator coverage_off*/
82 : output logic lsu_axi_bready,
83 : /*verilator coverage_on*/
84 2 : input logic [1:0] lsu_axi_bresp,
85 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
86 :
87 : // AXI Read Channels
88 630888 : output logic lsu_axi_arvalid,
89 673312 : input logic lsu_axi_arready,
90 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
91 282 : output logic [31:0] lsu_axi_araddr,
92 318 : output logic [3:0] lsu_axi_arregion,
93 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
94 : /*verilator coverage_off*/
95 : output logic [7:0] lsu_axi_arlen,
96 : /*verilator coverage_on*/
97 0 : output logic [2:0] lsu_axi_arsize,
98 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
99 : /*verilator coverage_off*/
100 : output logic [1:0] lsu_axi_arburst,
101 : output logic lsu_axi_arlock,
102 : /*verilator coverage_on*/
103 1773 : output logic [3:0] lsu_axi_arcache,
104 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
105 : /*verilator coverage_off*/
106 : output logic [2:0] lsu_axi_arprot,
107 : output logic [3:0] lsu_axi_arqos,
108 : /*verilator coverage_on*/
109 :
110 672996 : input logic lsu_axi_rvalid,
111 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
112 : /*verilator coverage_off*/
113 : output logic lsu_axi_rready,
114 : /*verilator coverage_on*/
115 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
116 26505 : input logic [63:0] lsu_axi_rdata,
117 2 : input logic [1:0] lsu_axi_rresp,
118 673648 : input logic lsu_axi_rlast,
119 :
120 : //-------------------------- IFU AXI signals--------------------------
121 : // AXI Write Channels
122 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
123 : /*verilator coverage_off*/
124 : output logic ifu_axi_awvalid,
125 : /*verilator coverage_on*/
126 0 : input logic ifu_axi_awready,
127 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
128 : /*verilator coverage_off*/
129 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
130 : output logic [31:0] ifu_axi_awaddr,
131 : output logic [3:0] ifu_axi_awregion,
132 : output logic [7:0] ifu_axi_awlen,
133 : output logic [2:0] ifu_axi_awsize,
134 : output logic [1:0] ifu_axi_awburst,
135 : output logic ifu_axi_awlock,
136 : output logic [3:0] ifu_axi_awcache,
137 : output logic [2:0] ifu_axi_awprot,
138 : output logic [3:0] ifu_axi_awqos,
139 :
140 : output logic ifu_axi_wvalid,
141 : /*verilator coverage_on*/
142 0 : input logic ifu_axi_wready,
143 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
144 : /*verilator coverage_off*/
145 : output logic [63:0] ifu_axi_wdata,
146 : output logic [7:0] ifu_axi_wstrb,
147 : output logic ifu_axi_wlast,
148 : /*verilator coverage_on*/
149 :
150 0 : input logic ifu_axi_bvalid,
151 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
152 : /*verilator coverage_off*/
153 : output logic ifu_axi_bready,
154 : /*verilator coverage_on*/
155 0 : input logic [1:0] ifu_axi_bresp,
156 0 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
157 :
158 : // AXI Read Channels
159 4449036 : output logic ifu_axi_arvalid,
160 8917946 : input logic ifu_axi_arready,
161 2738692 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
162 1937946 : output logic [31:0] ifu_axi_araddr,
163 456 : output logic [3:0] ifu_axi_arregion,
164 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
165 : /*verilator coverage_off*/
166 : output logic [7:0] ifu_axi_arlen,
167 : output logic [2:0] ifu_axi_arsize,
168 : output logic [1:0] ifu_axi_arburst,
169 : output logic ifu_axi_arlock,
170 : output logic [3:0] ifu_axi_arcache,
171 : output logic [2:0] ifu_axi_arprot,
172 : output logic [3:0] ifu_axi_arqos,
173 : /*verilator coverage_on*/
174 :
175 8917628 : input logic ifu_axi_rvalid,
176 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
177 : /*verilator coverage_off*/
178 : output logic ifu_axi_rready,
179 : /*verilator coverage_on*/
180 897349 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
181 744641 : input logic [63:0] ifu_axi_rdata,
182 20 : input logic [1:0] ifu_axi_rresp,
183 8917628 : input logic ifu_axi_rlast,
184 :
185 : //-------------------------- SB AXI signals--------------------------
186 : // AXI Write Channels
187 122 : output logic sb_axi_awvalid,
188 122 : input logic sb_axi_awready,
189 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
190 : /*verilator coverage_off*/
191 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
192 : /*verilator coverage_on*/
193 2 : output logic [31:0] sb_axi_awaddr,
194 98 : output logic [3:0] sb_axi_awregion,
195 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
196 : /*verilator coverage_off*/
197 : output logic [7:0] sb_axi_awlen,
198 : /*verilator coverage_on*/
199 0 : output logic [2:0] sb_axi_awsize,
200 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
201 : /*verilator coverage_off*/
202 : output logic [1:0] sb_axi_awburst,
203 : output logic sb_axi_awlock,
204 : output logic [3:0] sb_axi_awcache,
205 : output logic [2:0] sb_axi_awprot,
206 : output logic [3:0] sb_axi_awqos,
207 : /*verilator coverage_on*/
208 :
209 122 : output logic sb_axi_wvalid,
210 122 : input logic sb_axi_wready,
211 31 : output logic [63:0] sb_axi_wdata,
212 276 : output logic [7:0] sb_axi_wstrb,
213 319 : output logic sb_axi_wlast,
214 :
215 122 : input logic sb_axi_bvalid,
216 319 : output logic sb_axi_bready,
217 0 : input logic [1:0] sb_axi_bresp,
218 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
219 :
220 : // AXI Read Channels
221 652 : output logic sb_axi_arvalid,
222 652 : input logic sb_axi_arready,
223 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
224 : /*verilator coverage_off*/
225 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
226 : /*verilator coverage_on*/
227 2 : output logic [31:0] sb_axi_araddr,
228 98 : output logic [3:0] sb_axi_arregion,
229 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
230 : /*verilator coverage_off*/
231 : output logic [7:0] sb_axi_arlen,
232 : /*verilator coverage_on*/
233 0 : output logic [2:0] sb_axi_arsize,
234 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
235 : /*verilator coverage_off*/
236 : output logic [1:0] sb_axi_arburst,
237 : output logic sb_axi_arlock,
238 : output logic [3:0] sb_axi_arcache,
239 : output logic [2:0] sb_axi_arprot,
240 : output logic [3:0] sb_axi_arqos,
241 : /*verilator coverage_on*/
242 :
243 652 : input logic sb_axi_rvalid,
244 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
245 : /*verilator coverage_off*/
246 : output logic sb_axi_rready,
247 : /*verilator coverage_on*/
248 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
249 5 : input logic [63:0] sb_axi_rdata,
250 0 : input logic [1:0] sb_axi_rresp,
251 652 : input logic sb_axi_rlast,
252 :
253 : //-------------------------- DMA AXI signals--------------------------
254 : // AXI Write Channels
255 66 : input logic dma_axi_awvalid,
256 319 : output logic dma_axi_awready,
257 : /* exclude signals that are tied to constant value in tb_top.sv */
258 : /*verilator coverage_off*/
259 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
260 : /*verilator coverage_on*/
261 282 : input logic [31:0] dma_axi_awaddr,
262 0 : input logic [2:0] dma_axi_awsize,
263 0 : input logic [2:0] dma_axi_awprot,
264 0 : input logic [7:0] dma_axi_awlen,
265 0 : input logic [1:0] dma_axi_awburst,
266 :
267 :
268 66 : input logic dma_axi_wvalid,
269 319 : output logic dma_axi_wready,
270 29795 : input logic [63:0] dma_axi_wdata,
271 185761 : input logic [7:0] dma_axi_wstrb,
272 318 : input logic dma_axi_wlast,
273 :
274 66 : output logic dma_axi_bvalid,
275 66 : input logic dma_axi_bready,
276 2 : output logic [1:0] dma_axi_bresp,
277 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
278 :
279 : // AXI Read Channels
280 0 : input logic dma_axi_arvalid,
281 319 : output logic dma_axi_arready,
282 : /* exclude signals that are tied to constant value in tb_top.sv */
283 : /*verilator coverage_off*/
284 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
285 : /*verilator coverage_on*/
286 282 : input logic [31:0] dma_axi_araddr,
287 0 : input logic [2:0] dma_axi_arsize,
288 0 : input logic [2:0] dma_axi_arprot,
289 0 : input logic [7:0] dma_axi_arlen,
290 0 : input logic [1:0] dma_axi_arburst,
291 :
292 0 : output logic dma_axi_rvalid,
293 0 : input logic dma_axi_rready,
294 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
295 12 : output logic [63:0] dma_axi_rdata,
296 2 : output logic [1:0] dma_axi_rresp,
297 319 : output logic dma_axi_rlast,
298 : `endif
299 :
300 : `ifdef RV_BUILD_AHB_LITE
301 : //// AHB LITE BUS
302 17 : output logic [31:0] haddr,
303 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
304 : /*verilator coverage_off*/
305 : output logic [2:0] hburst,
306 : output logic hmastlock,
307 : /*verilator coverage_on*/
308 0 : output logic [3:0] hprot,
309 0 : output logic [2:0] hsize,
310 1445965 : output logic [1:0] htrans,
311 0 : output logic hwrite,
312 :
313 : /* exclude signals that are tied to constant value in this file */
314 : /*verilator coverage_off*/
315 : input logic [63:0] hrdata,
316 : input logic hready,
317 : input logic hresp,
318 : /*verilator coverage_on*/
319 :
320 : // LSU AHB Master
321 10 : output logic [31:0] lsu_haddr,
322 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
323 : /*verilator coverage_off*/
324 : output logic [2:0] lsu_hburst,
325 : output logic lsu_hmastlock,
326 : /*verilator coverage_on*/
327 0 : output logic [3:0] lsu_hprot,
328 0 : output logic [2:0] lsu_hsize,
329 445416 : output logic [1:0] lsu_htrans,
330 89186 : output logic lsu_hwrite,
331 5340 : output logic [63:0] lsu_hwdata,
332 :
333 : /* exclude signals that are tied to constant value in this file */
334 : /*verilator coverage_off*/
335 : input logic [63:0] lsu_hrdata,
336 : input logic lsu_hready,
337 : input logic lsu_hresp,
338 : /*verilator coverage_on*/
339 : // Debug Syster Bus AHB
340 2 : output logic [31:0] sb_haddr,
341 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
342 : /*verilator coverage_off*/
343 : output logic [2:0] sb_hburst,
344 : output logic sb_hmastlock,
345 : /*verilator coverage_on*/
346 0 : output logic [3:0] sb_hprot,
347 0 : output logic [2:0] sb_hsize,
348 974 : output logic [1:0] sb_htrans,
349 119 : output logic sb_hwrite,
350 35 : output logic [63:0] sb_hwdata,
351 :
352 : /* exclude signals that are tied to constant value in this file */
353 : /*verilator coverage_off*/
354 : input logic [63:0] sb_hrdata,
355 : input logic sb_hready,
356 : input logic sb_hresp,
357 : /*verilator coverage_on*/
358 :
359 : // DMA Slave
360 : /* exclude signals that are tied to constant value in tb_top.sv */
361 : /*verilator coverage_off*/
362 : input logic dma_hsel,
363 : input logic [31:0] dma_haddr,
364 : input logic [2:0] dma_hburst,
365 : input logic dma_hmastlock,
366 : input logic [3:0] dma_hprot,
367 : input logic [2:0] dma_hsize,
368 : input logic [1:0] dma_htrans,
369 : input logic dma_hwrite,
370 : input logic [63:0] dma_hwdata,
371 : /*verilator coverage_on*/
372 20 : input logic dma_hreadyin,
373 :
374 0 : output logic [63:0] dma_hrdata,
375 20 : output logic dma_hreadyout,
376 0 : output logic dma_hresp,
377 : `endif
378 : // clk ratio signals
379 338 : input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
380 338 : input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
381 338 : input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
382 338 : input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
383 :
384 : // ICCM/DCCM ECC status
385 8 : output logic iccm_ecc_single_error,
386 4 : output logic iccm_ecc_double_error,
387 4 : output logic dccm_ecc_single_error,
388 4 : output logic dccm_ecc_double_error,
389 :
390 : // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not)
391 :
392 0 : input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
393 0 : input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
394 :
395 18 : input logic timer_int,
396 19 : input logic soft_int,
397 0 : input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
398 :
399 340148 : output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
400 514626 : output logic dec_tlu_perfcnt1,
401 312914 : output logic dec_tlu_perfcnt2,
402 48468 : output logic dec_tlu_perfcnt3,
403 :
404 : // ports added by the soc team
405 1499062 : input logic jtag_tck, // JTAG clk
406 89840 : input logic jtag_tms, // JTAG TMS
407 115584 : input logic jtag_tdi, // JTAG tdi
408 4 : input logic jtag_trst_n, // JTAG Reset
409 113636 : output logic jtag_tdo, // JTAG TDO
410 44912 : output logic jtag_tdoEn, // JTAG Test Data Output enable
411 :
412 0 : input logic [31:4] core_id,
413 :
414 : // Memory Export Interface
415 : el2_mem_if.veer_sram_src el2_mem_export,
416 :
417 : // external MPC halt/run interface
418 108 : input logic mpc_debug_halt_req, // Async halt request
419 108 : input logic mpc_debug_run_req, // Async run request
420 338 : input logic mpc_reset_run_req, // Run/halt after reset
421 108 : output logic mpc_debug_halt_ack, // Halt ack
422 108 : output logic mpc_debug_run_ack, // Run ack
423 2 : output logic debug_brkpt_status, // debug breakpoint
424 :
425 108 : input logic i_cpu_halt_req, // Async halt req to CPU
426 108 : output logic o_cpu_halt_ack, // core response to halt
427 108 : output logic o_cpu_halt_status, // 1'b1 indicates core is halted
428 118 : output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
429 108 : input logic i_cpu_run_req, // Async restart req to CPU
430 108 : output logic o_cpu_run_ack, // Core response to run req
431 :
432 : /* exclude signals that are tied to constant value or left unconnected in tb_top.sv */
433 : /* verilator coverage_off */
434 : input logic scan_mode, // To enable scan mode
435 : input logic mbist_mode, // to enable mbist
436 :
437 : // DMI port for uncore
438 : input logic dmi_uncore_enable,
439 : output logic dmi_uncore_en,
440 : output logic dmi_uncore_wr_en,
441 : output logic [ 6:0] dmi_uncore_addr,
442 : output logic [31:0] dmi_uncore_wdata,
443 : input logic [31:0] dmi_uncore_rdata
444 : /* verilator coverage_on */
445 : );
446 :
447 69887189 : logic active_l2clk;
448 69887189 : logic free_l2clk;
449 :
450 : // DCCM ports
451 262894 : logic dccm_wren;
452 561000 : logic dccm_rden;
453 18811 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo;
454 18811 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi;
455 471334 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo;
456 677729 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi;
457 5376 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo;
458 5376 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi;
459 :
460 47176 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;
461 47176 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;
462 :
463 : // PIC ports
464 :
465 : // Icache & Itag ports
466 490 : logic [31:1] ic_rw_addr;
467 10432 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en ; // Which way to write
468 680962 : logic ic_rd_en ;
469 :
470 :
471 255918 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid; // Valid from the I$ tag valid outside (in flops).
472 :
473 109586 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit; // ic_rd_hit[3:0]
474 0 : logic ic_tag_perr; // Ic tag parity error
475 :
476 0 : logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr; // Read/Write addresss to the Icache.
477 0 : logic ic_debug_rd_en; // Icache debug rd
478 0 : logic ic_debug_wr_en; // Icache debug wr
479 0 : logic ic_debug_tag_array; // Debug tag array
480 0 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way; // Debug way. Rd or Wr.
481 :
482 0 : logic [25:0] ictag_debug_rd_data; // Debug icache tag.
483 560643 : logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
484 2137096 : logic [63:0] ic_rd_data;
485 231587 : logic [70:0] ic_debug_rd_data; // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
486 0 : logic [70:0] ic_debug_wr_data; // Debug wr cache.
487 :
488 0 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr; // ecc error per bank
489 0 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr; // parity error per bank
490 :
491 1738678 : logic [63:0] ic_premux_data;
492 5605501 : logic ic_sel_premux_data;
493 :
494 : // ICCM ports
495 160275 : logic [pt.ICCM_BITS-1:1] iccm_rw_addr;
496 74 : logic iccm_wren;
497 133206 : logic iccm_rden;
498 0 : logic [2:0] iccm_wr_size;
499 14 : logic [77:0] iccm_wr_data;
500 8 : logic iccm_buf_correct_ecc;
501 8 : logic iccm_correction_state;
502 :
503 136532 : logic [63:0] iccm_rd_data;
504 161264 : logic [77:0] iccm_rd_data_ecc;
505 :
506 338 : logic core_rst_l; // Core reset including rst_l and dbg_rst_l
507 :
508 2 : logic dccm_clk_override;
509 2 : logic icm_clk_override;
510 8 : logic dec_tlu_core_ecc_disable;
511 :
512 :
513 : // zero out the signals not presented at the wrapper instantiation level
514 : `ifdef RV_BUILD_AXI4
515 : // Since all the signals in this block are tied to constant, we exclude this from coverage analysis
516 : /*verilator coverage_off*/
517 :
518 : //// AHB LITE BUS
519 : logic [31:0] haddr;
520 : logic [2:0] hburst;
521 : logic hmastlock;
522 : logic [3:0] hprot;
523 : logic [2:0] hsize;
524 : logic [1:0] htrans;
525 : logic hwrite;
526 :
527 : logic [63:0] hrdata;
528 : logic hready;
529 : logic hresp;
530 :
531 : // LSU AHB Master
532 : logic [31:0] lsu_haddr;
533 : logic [2:0] lsu_hburst;
534 : logic lsu_hmastlock;
535 : logic [3:0] lsu_hprot;
536 : logic [2:0] lsu_hsize;
537 : logic [1:0] lsu_htrans;
538 : logic lsu_hwrite;
539 : logic [63:0] lsu_hwdata;
540 :
541 : logic [63:0] lsu_hrdata;
542 : logic lsu_hready;
543 : logic lsu_hresp;
544 : // Debug Syster Bus AHB
545 : logic [31:0] sb_haddr;
546 : logic [2:0] sb_hburst;
547 : logic sb_hmastlock;
548 : logic [3:0] sb_hprot;
549 : logic [2:0] sb_hsize;
550 : logic [1:0] sb_htrans;
551 : logic sb_hwrite;
552 : logic [63:0] sb_hwdata;
553 :
554 : logic [63:0] sb_hrdata;
555 : logic sb_hready;
556 : logic sb_hresp;
557 :
558 : // DMA Slave
559 : logic dma_hsel;
560 : logic [31:0] dma_haddr;
561 : logic [2:0] dma_hburst;
562 : logic dma_hmastlock;
563 : logic [3:0] dma_hprot;
564 : logic [2:0] dma_hsize;
565 : logic [1:0] dma_htrans;
566 : logic dma_hwrite;
567 : logic [63:0] dma_hwdata;
568 : logic dma_hreadyin;
569 :
570 : logic [63:0] dma_hrdata;
571 : logic dma_hreadyout;
572 : logic dma_hresp;
573 :
574 :
575 :
576 : // AHB
577 : assign hrdata[63:0] = '0;
578 : assign hready = '0;
579 : assign hresp = '0;
580 : // LSU
581 : assign lsu_hrdata[63:0] = '0;
582 : assign lsu_hready = '0;
583 : assign lsu_hresp = '0;
584 : // Debu
585 : assign sb_hrdata[63:0] = '0;
586 : assign sb_hready = '0;
587 : assign sb_hresp = '0;
588 :
589 : // DMA
590 : assign dma_hsel = '0;
591 : assign dma_haddr[31:0] = '0;
592 : assign dma_hburst[2:0] = '0;
593 : assign dma_hmastlock = '0;
594 : assign dma_hprot[3:0] = '0;
595 : assign dma_hsize[2:0] = '0;
596 : assign dma_htrans[1:0] = '0;
597 : assign dma_hwrite = '0;
598 : assign dma_hwdata[63:0] = '0;
599 : assign dma_hreadyin = '0;
600 :
601 : /*verilator coverage_on*/
602 :
603 : `endif // `ifdef RV_BUILD_AXI4
604 :
605 :
606 : `ifdef RV_BUILD_AHB_LITE
607 : // Since all the signals in this block are tied to constant, we exclude this from coverage analysis
608 : /*verilator coverage_off*/
609 : wire lsu_axi_awvalid;
610 : wire lsu_axi_awready;
611 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;
612 : wire [31:0] lsu_axi_awaddr;
613 : wire [3:0] lsu_axi_awregion;
614 : wire [7:0] lsu_axi_awlen;
615 : wire [2:0] lsu_axi_awsize;
616 : wire [1:0] lsu_axi_awburst;
617 : wire lsu_axi_awlock;
618 : wire [3:0] lsu_axi_awcache;
619 : wire [2:0] lsu_axi_awprot;
620 : wire [3:0] lsu_axi_awqos;
621 :
622 :
623 : wire lsu_axi_wvalid;
624 : wire lsu_axi_wready;
625 : wire [63:0] lsu_axi_wdata;
626 : wire [7:0] lsu_axi_wstrb;
627 : wire lsu_axi_wlast;
628 :
629 : wire lsu_axi_bvalid;
630 : wire lsu_axi_bready;
631 : wire [1:0] lsu_axi_bresp;
632 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;
633 :
634 : // AXI Read Channels
635 : wire lsu_axi_arvalid;
636 : wire lsu_axi_arready;
637 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;
638 : wire [31:0] lsu_axi_araddr;
639 : wire [3:0] lsu_axi_arregion;
640 : wire [7:0] lsu_axi_arlen;
641 : wire [2:0] lsu_axi_arsize;
642 : wire [1:0] lsu_axi_arburst;
643 : wire lsu_axi_arlock;
644 : wire [3:0] lsu_axi_arcache;
645 : wire [2:0] lsu_axi_arprot;
646 : wire [3:0] lsu_axi_arqos;
647 :
648 : wire lsu_axi_rvalid;
649 : wire lsu_axi_rready;
650 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;
651 : wire [63:0] lsu_axi_rdata;
652 : wire [1:0] lsu_axi_rresp;
653 : wire lsu_axi_rlast;
654 :
655 : assign lsu_axi_awready = '0;
656 : assign lsu_axi_wready = '0;
657 : assign lsu_axi_bvalid = '0;
658 : assign lsu_axi_bresp = '0;
659 : assign lsu_axi_bid = {pt.LSU_BUS_TAG{1'b0}};
660 : assign lsu_axi_arready = '0;
661 : assign lsu_axi_rvalid = '0;
662 : assign lsu_axi_rid = {pt.LSU_BUS_TAG{1'b0}};
663 : assign lsu_axi_rdata = '0;
664 : assign lsu_axi_rresp = '0;
665 : assign lsu_axi_rlast = '0;
666 : //-------------------------- IFU AXI signals--------------------------
667 : // AXI Write Channels
668 : wire ifu_axi_awvalid;
669 : wire ifu_axi_awready;
670 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;
671 : wire [31:0] ifu_axi_awaddr;
672 : wire [3:0] ifu_axi_awregion;
673 : wire [7:0] ifu_axi_awlen;
674 : wire [2:0] ifu_axi_awsize;
675 : wire [1:0] ifu_axi_awburst;
676 : wire ifu_axi_awlock;
677 : wire [3:0] ifu_axi_awcache;
678 : wire [2:0] ifu_axi_awprot;
679 : wire [3:0] ifu_axi_awqos;
680 :
681 : wire ifu_axi_wvalid;
682 : wire ifu_axi_wready;
683 : wire [63:0] ifu_axi_wdata;
684 : wire [7:0] ifu_axi_wstrb;
685 : wire ifu_axi_wlast;
686 :
687 : wire ifu_axi_bvalid;
688 : wire ifu_axi_bready;
689 : wire [1:0] ifu_axi_bresp;
690 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_bid;
691 :
692 : // AXI Read Channels
693 : wire ifu_axi_arvalid;
694 : wire ifu_axi_arready;
695 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_arid;
696 : wire [31:0] ifu_axi_araddr;
697 : wire [3:0] ifu_axi_arregion;
698 : wire [7:0] ifu_axi_arlen;
699 : wire [2:0] ifu_axi_arsize;
700 : wire [1:0] ifu_axi_arburst;
701 : wire ifu_axi_arlock;
702 : wire [3:0] ifu_axi_arcache;
703 : wire [2:0] ifu_axi_arprot;
704 : wire [3:0] ifu_axi_arqos;
705 :
706 : wire ifu_axi_rvalid;
707 : wire ifu_axi_rready;
708 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_rid;
709 : wire [63:0] ifu_axi_rdata;
710 : wire [1:0] ifu_axi_rresp;
711 : wire ifu_axi_rlast;
712 :
713 : assign ifu_axi_bvalid = '0;
714 : assign ifu_axi_bresp = '0;
715 : assign ifu_axi_bid = {pt.IFU_BUS_TAG{1'b0}};
716 : assign ifu_axi_arready = '0;
717 : assign ifu_axi_rvalid = '0;
718 : assign ifu_axi_rid = {pt.IFU_BUS_TAG{1'b0}};
719 : assign ifu_axi_rdata = 0;
720 : assign ifu_axi_rresp = '0;
721 : assign ifu_axi_rlast = '0;
722 : //-------------------------- SB AXI signals--------------------------
723 : // AXI Write Channels
724 : wire sb_axi_awvalid;
725 : wire sb_axi_awready;
726 : wire [pt.SB_BUS_TAG-1:0] sb_axi_awid;
727 : wire [31:0] sb_axi_awaddr;
728 : wire [3:0] sb_axi_awregion;
729 : wire [7:0] sb_axi_awlen;
730 : wire [2:0] sb_axi_awsize;
731 : wire [1:0] sb_axi_awburst;
732 : wire sb_axi_awlock;
733 : wire [3:0] sb_axi_awcache;
734 : wire [2:0] sb_axi_awprot;
735 : wire [3:0] sb_axi_awqos;
736 :
737 : wire sb_axi_wvalid;
738 : wire sb_axi_wready;
739 : wire [63:0] sb_axi_wdata;
740 : wire [7:0] sb_axi_wstrb;
741 : wire sb_axi_wlast;
742 :
743 : wire sb_axi_bvalid;
744 : wire sb_axi_bready;
745 : wire [1:0] sb_axi_bresp;
746 : wire [pt.SB_BUS_TAG-1:0] sb_axi_bid;
747 :
748 : // AXI Read Channels
749 : wire sb_axi_arvalid;
750 : wire sb_axi_arready;
751 : wire [pt.SB_BUS_TAG-1:0] sb_axi_arid;
752 : wire [31:0] sb_axi_araddr;
753 : wire [3:0] sb_axi_arregion;
754 : wire [7:0] sb_axi_arlen;
755 : wire [2:0] sb_axi_arsize;
756 : wire [1:0] sb_axi_arburst;
757 : wire sb_axi_arlock;
758 : wire [3:0] sb_axi_arcache;
759 : wire [2:0] sb_axi_arprot;
760 : wire [3:0] sb_axi_arqos;
761 :
762 : wire sb_axi_rvalid;
763 : wire sb_axi_rready;
764 : wire [pt.SB_BUS_TAG-1:0] sb_axi_rid;
765 : wire [63:0] sb_axi_rdata;
766 : wire [1:0] sb_axi_rresp;
767 : wire sb_axi_rlast;
768 :
769 : assign sb_axi_awready = '0;
770 : assign sb_axi_wready = '0;
771 : assign sb_axi_bvalid = '0;
772 : assign sb_axi_bresp = '0;
773 : assign sb_axi_bid = {pt.SB_BUS_TAG{1'b0}};
774 : assign sb_axi_arready = '0;
775 : assign sb_axi_rvalid = '0;
776 : assign sb_axi_rid = {pt.SB_BUS_TAG{1'b0}};
777 : assign sb_axi_rdata = '0;
778 : assign sb_axi_rresp = '0;
779 : assign sb_axi_rlast = '0;
780 : //-------------------------- DMA AXI signals--------------------------
781 : // AXI Write Channels
782 : wire dma_axi_awvalid;
783 : wire dma_axi_awready;
784 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_awid;
785 : wire [31:0] dma_axi_awaddr;
786 : wire [2:0] dma_axi_awsize;
787 : wire [2:0] dma_axi_awprot;
788 : wire [7:0] dma_axi_awlen;
789 : wire [1:0] dma_axi_awburst;
790 :
791 :
792 : wire dma_axi_wvalid;
793 : wire dma_axi_wready;
794 : wire [63:0] dma_axi_wdata;
795 : wire [7:0] dma_axi_wstrb;
796 : wire dma_axi_wlast;
797 :
798 : assign dma_axi_awvalid = 1'b0;
799 : assign dma_axi_awid = {pt.DMA_BUS_TAG{1'b0}};
800 : assign dma_axi_awaddr = 32'd0;
801 : assign dma_axi_awsize = 3'd0;
802 : assign dma_axi_awprot = 3'd0;
803 : assign dma_axi_awlen = 8'd0;
804 : assign dma_axi_awburst = 2'd0;
805 :
806 :
807 : assign dma_axi_wvalid = 1'b0;
808 : assign dma_axi_wdata = 64'd0;
809 : assign dma_axi_wstrb = 8'd0;
810 : assign dma_axi_wlast = 1'b0;
811 :
812 :
813 : wire dma_axi_bvalid;
814 : wire dma_axi_bready;
815 : wire [1:0] dma_axi_bresp;
816 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_bid;
817 :
818 : assign dma_axi_bready = 1'b0;
819 : // AXI Read Channels
820 : wire dma_axi_arvalid;
821 : wire dma_axi_arready;
822 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_arid;
823 : wire [31:0] dma_axi_araddr;
824 : wire [2:0] dma_axi_arsize;
825 : wire [2:0] dma_axi_arprot;
826 : wire [7:0] dma_axi_arlen;
827 : wire [1:0] dma_axi_arburst;
828 :
829 : assign dma_axi_arvalid = 1'b0;
830 : assign dma_axi_arid = {pt.DMA_BUS_TAG{1'b0}};
831 : assign dma_axi_araddr = 32'd0;
832 : assign dma_axi_arsize = 3'd0;
833 : assign dma_axi_arprot = 3'd0;
834 : assign dma_axi_arlen = 8'd0;
835 : assign dma_axi_arburst = 2'd0;
836 :
837 :
838 :
839 : wire dma_axi_rvalid;
840 : wire dma_axi_rready;
841 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_rid;
842 : wire [63:0] dma_axi_rdata;
843 : wire [1:0] dma_axi_rresp;
844 : wire dma_axi_rlast;
845 :
846 : assign dma_axi_rready = 1'b0;
847 : // AXI
848 : assign ifu_axi_awready = 1'b1;
849 : assign ifu_axi_wready = 1'b1;
850 : assign ifu_axi_bvalid = '0;
851 : assign ifu_axi_bresp[1:0] = '0;
852 : assign ifu_axi_bid[pt.IFU_BUS_TAG-1:0] = '0;
853 :
854 : /*verilator coverage_on*/
855 :
856 : `endif // `ifdef RV_BUILD_AHB_LITE
857 :
858 : // DMI (core)
859 16322 : logic dmi_en;
860 0 : logic [6:0] dmi_addr;
861 6018 : logic dmi_wr_en;
862 80 : logic [31:0] dmi_wdata;
863 106 : logic [31:0] dmi_rdata;
864 :
865 : // DMI (core)
866 16322 : logic dmi_reg_en;
867 0 : logic [6:0] dmi_reg_addr;
868 6018 : logic dmi_reg_wr_en;
869 80 : logic [31:0] dmi_reg_wdata;
870 106 : logic [31:0] dmi_reg_rdata;
871 :
872 : // Instantiate the el2_veer core
873 : el2_veer #(.pt(pt)) veer (
874 : .clk(clk),
875 : .*
876 : );
877 :
878 : // Instantiate the mem
879 : el2_mem #(.pt(pt)) mem (
880 : .clk(active_l2clk),
881 : .rst_l(core_rst_l),
882 : .mem_export(el2_mem_export),
883 : .*
884 : );
885 :
886 :
887 : // JTAG/DMI instance
888 : dmi_wrapper dmi_wrapper (
889 : // JTAG signals
890 : .trst_n (jtag_trst_n), // JTAG reset
891 : .tck (jtag_tck), // JTAG clock
892 : .tms (jtag_tms), // Test mode select
893 : .tdi (jtag_tdi), // Test Data Input
894 : .tdo (jtag_tdo), // Test Data Output
895 : .tdoEnable (jtag_tdoEn), // Test Data Output enable
896 : // Processor Signals
897 : .core_rst_n (dbg_rst_l), // Debug reset, active low
898 : .core_clk (clk), // Core clock
899 : .jtag_id (jtag_id), // JTAG ID
900 : .rd_data (dmi_rdata), // Read data from Processor
901 : .reg_wr_data (dmi_wdata), // Write data to Processor
902 : .reg_wr_addr (dmi_addr), // Write address to Processor
903 : .reg_en (dmi_en), // Write interface bit to Processor
904 : .reg_wr_en (dmi_wr_en), // Write enable to Processor
905 : .dmi_hard_reset ()
906 : );
907 :
908 : // DMI core/uncore mux
909 : dmi_mux dmi_mux (
910 : .uncore_enable (dmi_uncore_enable),
911 :
912 : .dmi_en (dmi_en),
913 : .dmi_wr_en (dmi_wr_en),
914 : .dmi_addr (dmi_addr),
915 : .dmi_wdata (dmi_wdata),
916 : .dmi_rdata (dmi_rdata),
917 :
918 : .dmi_core_en (dmi_reg_en),
919 : .dmi_core_wr_en (dmi_reg_wr_en),
920 : .dmi_core_addr (dmi_reg_addr),
921 : .dmi_core_wdata (dmi_reg_wdata),
922 : .dmi_core_rdata (dmi_reg_rdata),
923 :
924 : .dmi_uncore_en (dmi_uncore_en),
925 : .dmi_uncore_wr_en (dmi_uncore_wr_en),
926 : .dmi_uncore_addr (dmi_uncore_addr),
927 : .dmi_uncore_wdata (dmi_uncore_wdata),
928 : .dmi_uncore_rdata (dmi_uncore_rdata)
929 : );
930 :
931 : `ifdef RV_ASSERT_ON
932 : // to avoid internal assertions failure at time 0
933 : initial begin
934 : $assertoff(0, veer);
935 : @(negedge clk) $asserton(0, veer);
936 : end
937 : `endif
938 :
939 : endmodule
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