Line data Source code
1 : // Copyright 2024 Antmicro <www.antmicro.com>
2 : //
3 : // SPDX-License-Identifier: Apache-2.0
4 :
5 : module el2_veer_lockstep
6 : import el2_pkg::*;
7 : #(
8 : `include "el2_param.vh"
9 : ) (
10 : `ifdef RV_LOCKSTEP_REGFILE_ENABLE
11 : el2_regfile_if.veer_rf_sink main_core_regfile,
12 : `endif
13 :
14 91 : input logic clk,
15 3 : input logic rst_l,
16 3 : input logic dbg_rst_l,
17 0 : input logic [31:1] rst_vec,
18 0 : input logic nmi_int,
19 0 : input logic [31:1] nmi_vec,
20 3 : input logic core_rst_l, // This is "rst_l | dbg_rst_l"
21 :
22 91 : input logic active_l2clk,
23 91 : input logic free_l2clk,
24 :
25 0 : input logic [31:0] trace_rv_i_insn_ip,
26 0 : input logic [31:0] trace_rv_i_address_ip,
27 0 : input logic trace_rv_i_valid_ip,
28 0 : input logic trace_rv_i_exception_ip,
29 0 : input logic [4:0] trace_rv_i_ecause_ip,
30 0 : input logic trace_rv_i_interrupt_ip,
31 0 : input logic [31:0] trace_rv_i_tval_ip,
32 :
33 :
34 0 : input logic dccm_clk_override,
35 0 : input logic icm_clk_override,
36 0 : input logic dec_tlu_core_ecc_disable,
37 :
38 : // external halt/run interface
39 0 : input logic i_cpu_halt_req, // Asynchronous Halt request to CPU
40 0 : input logic i_cpu_run_req, // Asynchronous Restart request to CPU
41 0 : input logic o_cpu_halt_ack, // Core Acknowledge to Halt request
42 0 : input logic o_cpu_halt_status, // 1'b1 indicates processor is halted
43 0 : input logic o_cpu_run_ack, // Core Acknowledge to run request
44 3 : input logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
45 :
46 0 : input logic [31:4] core_id, // CORE ID
47 :
48 : // external MPC halt/run interface
49 0 : input logic mpc_debug_halt_req, // Async halt request
50 0 : input logic mpc_debug_run_req, // Async run request
51 0 : input logic mpc_reset_run_req, // Run/halt after reset
52 0 : input logic mpc_debug_halt_ack, // Halt ack
53 0 : input logic mpc_debug_run_ack, // Run ack
54 0 : input logic debug_brkpt_status, // debug breakpoint
55 :
56 0 : input logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
57 0 : input logic dec_tlu_perfcnt1,
58 0 : input logic dec_tlu_perfcnt2,
59 0 : input logic dec_tlu_perfcnt3,
60 :
61 : // DCCM ports
62 0 : input logic dccm_wren,
63 0 : input logic dccm_rden,
64 0 : input logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
65 0 : input logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
66 0 : input logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
67 0 : input logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
68 0 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
69 0 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
70 :
71 0 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
72 0 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
73 :
74 : // ICCM ports
75 0 : input logic [pt.ICCM_BITS-1:1] iccm_rw_addr,
76 0 : input logic iccm_wren,
77 0 : input logic iccm_rden,
78 0 : input logic [ 2:0] iccm_wr_size,
79 0 : input logic [ 77:0] iccm_wr_data,
80 0 : input logic iccm_buf_correct_ecc,
81 0 : input logic iccm_correction_state,
82 :
83 0 : input logic [63:0] iccm_rd_data,
84 0 : input logic [77:0] iccm_rd_data_ecc,
85 :
86 : // ICache , ITAG ports
87 0 : input logic [ 31:1] ic_rw_addr,
88 0 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,
89 0 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,
90 0 : input logic ic_rd_en,
91 :
92 0 : input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
93 0 : input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
94 0 : input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
95 0 : input logic [25:0] ictag_debug_rd_data, // Debug icache tag.
96 0 : input logic [70:0] ic_debug_wr_data, // Debug wr cache.
97 :
98 0 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
99 0 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
100 0 : input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
101 0 : input logic ic_sel_premux_data, // Select premux data
102 :
103 :
104 0 : input logic [ pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
105 0 : input logic ic_debug_rd_en, // Icache debug rd
106 0 : input logic ic_debug_wr_en, // Icache debug wr
107 0 : input logic ic_debug_tag_array, // Debug tag array
108 0 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
109 :
110 :
111 0 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
112 0 : input logic ic_tag_perr, // Icache Tag parity error
113 :
114 : //-------------------------- LSU AXI signals--------------------------
115 : // AXI Write Channels
116 0 : input logic lsu_axi_awvalid,
117 0 : input logic lsu_axi_awready,
118 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
119 0 : input logic [ 31:0] lsu_axi_awaddr,
120 0 : input logic [ 3:0] lsu_axi_awregion,
121 0 : input logic [ 7:0] lsu_axi_awlen,
122 0 : input logic [ 2:0] lsu_axi_awsize,
123 0 : input logic [ 1:0] lsu_axi_awburst,
124 0 : input logic lsu_axi_awlock,
125 1 : input logic [ 3:0] lsu_axi_awcache,
126 0 : input logic [ 2:0] lsu_axi_awprot,
127 0 : input logic [ 3:0] lsu_axi_awqos,
128 :
129 0 : input logic lsu_axi_wvalid,
130 0 : input logic lsu_axi_wready,
131 0 : input logic [63:0] lsu_axi_wdata,
132 0 : input logic [ 7:0] lsu_axi_wstrb,
133 1 : input logic lsu_axi_wlast,
134 :
135 0 : input logic lsu_axi_bvalid,
136 1 : input logic lsu_axi_bready,
137 0 : input logic [ 1:0] lsu_axi_bresp,
138 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
139 :
140 : // AXI Read Channels
141 0 : input logic lsu_axi_arvalid,
142 0 : input logic lsu_axi_arready,
143 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
144 0 : input logic [ 31:0] lsu_axi_araddr,
145 0 : input logic [ 3:0] lsu_axi_arregion,
146 0 : input logic [ 7:0] lsu_axi_arlen,
147 0 : input logic [ 2:0] lsu_axi_arsize,
148 0 : input logic [ 1:0] lsu_axi_arburst,
149 0 : input logic lsu_axi_arlock,
150 1 : input logic [ 3:0] lsu_axi_arcache,
151 0 : input logic [ 2:0] lsu_axi_arprot,
152 0 : input logic [ 3:0] lsu_axi_arqos,
153 :
154 0 : input logic lsu_axi_rvalid,
155 1 : input logic lsu_axi_rready,
156 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
157 0 : input logic [ 63:0] lsu_axi_rdata,
158 0 : input logic [ 1:0] lsu_axi_rresp,
159 0 : input logic lsu_axi_rlast,
160 :
161 : //-------------------------- IFU AXI signals--------------------------
162 : // AXI Write Channels
163 0 : input logic ifu_axi_awvalid,
164 0 : input logic ifu_axi_awready,
165 0 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
166 0 : input logic [ 31:0] ifu_axi_awaddr,
167 0 : input logic [ 3:0] ifu_axi_awregion,
168 0 : input logic [ 7:0] ifu_axi_awlen,
169 0 : input logic [ 2:0] ifu_axi_awsize,
170 0 : input logic [ 1:0] ifu_axi_awburst,
171 0 : input logic ifu_axi_awlock,
172 0 : input logic [ 3:0] ifu_axi_awcache,
173 0 : input logic [ 2:0] ifu_axi_awprot,
174 0 : input logic [ 3:0] ifu_axi_awqos,
175 :
176 0 : input logic ifu_axi_wvalid,
177 0 : input logic ifu_axi_wready,
178 0 : input logic [63:0] ifu_axi_wdata,
179 0 : input logic [ 7:0] ifu_axi_wstrb,
180 0 : input logic ifu_axi_wlast,
181 :
182 0 : input logic ifu_axi_bvalid,
183 0 : input logic ifu_axi_bready,
184 0 : input logic [ 1:0] ifu_axi_bresp,
185 0 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
186 :
187 : // AXI Read Channels
188 0 : input logic ifu_axi_arvalid,
189 0 : input logic ifu_axi_arready,
190 0 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
191 0 : input logic [ 31:0] ifu_axi_araddr,
192 0 : input logic [ 3:0] ifu_axi_arregion,
193 0 : input logic [ 7:0] ifu_axi_arlen,
194 0 : input logic [ 2:0] ifu_axi_arsize,
195 0 : input logic [ 1:0] ifu_axi_arburst,
196 0 : input logic ifu_axi_arlock,
197 1 : input logic [ 3:0] ifu_axi_arcache,
198 1 : input logic [ 2:0] ifu_axi_arprot,
199 0 : input logic [ 3:0] ifu_axi_arqos,
200 :
201 0 : input logic ifu_axi_rvalid,
202 1 : input logic ifu_axi_rready,
203 0 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
204 0 : input logic [ 63:0] ifu_axi_rdata,
205 0 : input logic [ 1:0] ifu_axi_rresp,
206 0 : input logic ifu_axi_rlast,
207 :
208 : //-------------------------- SB AXI signals--------------------------
209 : // AXI Write Channels
210 0 : input logic sb_axi_awvalid,
211 0 : input logic sb_axi_awready,
212 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
213 0 : input logic [ 31:0] sb_axi_awaddr,
214 0 : input logic [ 3:0] sb_axi_awregion,
215 0 : input logic [ 7:0] sb_axi_awlen,
216 0 : input logic [ 2:0] sb_axi_awsize,
217 0 : input logic [ 1:0] sb_axi_awburst,
218 0 : input logic sb_axi_awlock,
219 1 : input logic [ 3:0] sb_axi_awcache,
220 0 : input logic [ 2:0] sb_axi_awprot,
221 0 : input logic [ 3:0] sb_axi_awqos,
222 :
223 0 : input logic sb_axi_wvalid,
224 0 : input logic sb_axi_wready,
225 0 : input logic [63:0] sb_axi_wdata,
226 0 : input logic [ 7:0] sb_axi_wstrb,
227 1 : input logic sb_axi_wlast,
228 :
229 0 : input logic sb_axi_bvalid,
230 1 : input logic sb_axi_bready,
231 0 : input logic [ 1:0] sb_axi_bresp,
232 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
233 :
234 : // AXI Read Channels
235 0 : input logic sb_axi_arvalid,
236 0 : input logic sb_axi_arready,
237 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
238 0 : input logic [ 31:0] sb_axi_araddr,
239 0 : input logic [ 3:0] sb_axi_arregion,
240 0 : input logic [ 7:0] sb_axi_arlen,
241 0 : input logic [ 2:0] sb_axi_arsize,
242 0 : input logic [ 1:0] sb_axi_arburst,
243 0 : input logic sb_axi_arlock,
244 0 : input logic [ 3:0] sb_axi_arcache,
245 0 : input logic [ 2:0] sb_axi_arprot,
246 0 : input logic [ 3:0] sb_axi_arqos,
247 :
248 0 : input logic sb_axi_rvalid,
249 1 : input logic sb_axi_rready,
250 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
251 0 : input logic [ 63:0] sb_axi_rdata,
252 0 : input logic [ 1:0] sb_axi_rresp,
253 0 : input logic sb_axi_rlast,
254 :
255 : //-------------------------- DMA AXI signals--------------------------
256 : // AXI Write Channels
257 0 : input logic dma_axi_awvalid,
258 1 : input logic dma_axi_awready,
259 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
260 0 : input logic [ 31:0] dma_axi_awaddr,
261 0 : input logic [ 2:0] dma_axi_awsize,
262 0 : input logic [ 2:0] dma_axi_awprot,
263 0 : input logic [ 7:0] dma_axi_awlen,
264 0 : input logic [ 1:0] dma_axi_awburst,
265 :
266 :
267 0 : input logic dma_axi_wvalid,
268 1 : input logic dma_axi_wready,
269 0 : input logic [63:0] dma_axi_wdata,
270 0 : input logic [ 7:0] dma_axi_wstrb,
271 0 : input logic dma_axi_wlast,
272 :
273 0 : input logic dma_axi_bvalid,
274 0 : input logic dma_axi_bready,
275 0 : input logic [ 1:0] dma_axi_bresp,
276 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
277 :
278 : // AXI Read Channels
279 0 : input logic dma_axi_arvalid,
280 1 : input logic dma_axi_arready,
281 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
282 0 : input logic [ 31:0] dma_axi_araddr,
283 0 : input logic [ 2:0] dma_axi_arsize,
284 0 : input logic [ 2:0] dma_axi_arprot,
285 0 : input logic [ 7:0] dma_axi_arlen,
286 0 : input logic [ 1:0] dma_axi_arburst,
287 :
288 0 : input logic dma_axi_rvalid,
289 0 : input logic dma_axi_rready,
290 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
291 0 : input logic [ 63:0] dma_axi_rdata,
292 0 : input logic [ 1:0] dma_axi_rresp,
293 1 : input logic dma_axi_rlast,
294 :
295 :
296 : //// AHB LITE BUS
297 0 : input logic [31:0] haddr,
298 0 : input logic [ 2:0] hburst,
299 0 : input logic hmastlock,
300 0 : input logic [ 3:0] hprot,
301 0 : input logic [ 2:0] hsize,
302 0 : input logic [ 1:0] htrans,
303 0 : input logic hwrite,
304 :
305 0 : input logic [63:0] hrdata,
306 0 : input logic hready,
307 0 : input logic hresp,
308 :
309 : // LSU AHB Master
310 0 : input logic [31:0] lsu_haddr,
311 0 : input logic [ 2:0] lsu_hburst,
312 0 : input logic lsu_hmastlock,
313 0 : input logic [ 3:0] lsu_hprot,
314 0 : input logic [ 2:0] lsu_hsize,
315 0 : input logic [ 1:0] lsu_htrans,
316 0 : input logic lsu_hwrite,
317 0 : input logic [63:0] lsu_hwdata,
318 :
319 0 : input logic [63:0] lsu_hrdata,
320 0 : input logic lsu_hready,
321 0 : input logic lsu_hresp,
322 :
323 : //System Bus Debug Master
324 0 : input logic [31:0] sb_haddr,
325 0 : input logic [ 2:0] sb_hburst,
326 0 : input logic sb_hmastlock,
327 0 : input logic [ 3:0] sb_hprot,
328 0 : input logic [ 2:0] sb_hsize,
329 0 : input logic [ 1:0] sb_htrans,
330 0 : input logic sb_hwrite,
331 0 : input logic [63:0] sb_hwdata,
332 :
333 0 : input logic [63:0] sb_hrdata,
334 0 : input logic sb_hready,
335 0 : input logic sb_hresp,
336 :
337 : // DMA Slave
338 0 : input logic dma_hsel,
339 0 : input logic [31:0] dma_haddr,
340 0 : input logic [ 2:0] dma_hburst,
341 0 : input logic dma_hmastlock,
342 0 : input logic [ 3:0] dma_hprot,
343 0 : input logic [ 2:0] dma_hsize,
344 0 : input logic [ 1:0] dma_htrans,
345 0 : input logic dma_hwrite,
346 0 : input logic [63:0] dma_hwdata,
347 0 : input logic dma_hreadyin,
348 :
349 0 : input logic [63:0] dma_hrdata,
350 0 : input logic dma_hreadyout,
351 0 : input logic dma_hresp,
352 :
353 0 : input logic lsu_bus_clk_en,
354 0 : input logic ifu_bus_clk_en,
355 0 : input logic dbg_bus_clk_en,
356 0 : input logic dma_bus_clk_en,
357 :
358 0 : input logic dmi_reg_en, // read or write
359 0 : input logic [ 6:0] dmi_reg_addr, // address of DM register
360 0 : input logic dmi_reg_wr_en, // write instruction
361 0 : input logic [31:0] dmi_reg_wdata, // write data
362 0 : input logic [31:0] dmi_reg_rdata,
363 :
364 : // ICCM/DCCM ECC status
365 0 : input logic iccm_ecc_single_error,
366 0 : input logic iccm_ecc_double_error,
367 0 : input logic dccm_ecc_single_error,
368 0 : input logic dccm_ecc_double_error,
369 :
370 0 : input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
371 0 : input logic timer_int,
372 0 : input logic soft_int,
373 0 : input logic scan_mode,
374 :
375 : // Shadow Core control
376 1 : input logic disable_corruption_detection_i,
377 1 : input logic lockstep_err_injection_en_i,
378 :
379 : // Equivalency Checker output
380 2 : output logic corruption_detected_o
381 : );
382 :
383 : localparam int unsigned LockstepDelay = int'(pt.LOCKSTEP_DELAY); // Delay I/O; in clock cycles
384 :
385 : // Outputs
386 : typedef struct packed {
387 : logic core_rst_l;
388 : logic [31:0] trace_rv_i_insn_ip;
389 : logic [31:0] trace_rv_i_address_ip;
390 : logic trace_rv_i_valid_ip;
391 : logic trace_rv_i_exception_ip;
392 : logic [4:0] trace_rv_i_ecause_ip;
393 : logic trace_rv_i_interrupt_ip;
394 : logic [31:0] trace_rv_i_tval_ip;
395 : logic dccm_clk_override;
396 : logic icm_clk_override;
397 : logic dec_tlu_core_ecc_disable;
398 : logic o_cpu_halt_ack;
399 : logic o_cpu_halt_status;
400 : logic o_cpu_run_ack;
401 : logic o_debug_mode_status;
402 : logic mpc_debug_halt_ack;
403 : logic mpc_debug_run_ack;
404 : logic debug_brkpt_status;
405 : logic dec_tlu_perfcnt0;
406 : logic dec_tlu_perfcnt1;
407 : logic dec_tlu_perfcnt2;
408 : logic dec_tlu_perfcnt3;
409 : logic dccm_wren;
410 : logic dccm_rden;
411 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo;
412 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi;
413 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo;
414 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi;
415 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo;
416 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi;
417 : logic [pt.ICCM_BITS-1:1] iccm_rw_addr;
418 : logic iccm_wren;
419 : logic iccm_rden;
420 : logic [2:0] iccm_wr_size;
421 : logic [77:0] iccm_wr_data;
422 : logic iccm_buf_correct_ecc;
423 : logic iccm_correction_state;
424 : logic [31:1] ic_rw_addr;
425 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid;
426 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en;
427 : logic ic_rd_en;
428 : logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
429 : logic [70:0] ic_debug_wr_data;
430 : logic [63:0] ic_premux_data;
431 : logic ic_sel_premux_data;
432 : logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr;
433 : logic ic_debug_rd_en;
434 : logic ic_debug_wr_en;
435 : logic ic_debug_tag_array;
436 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way;
437 : logic lsu_axi_awvalid;
438 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;
439 : logic [31:0] lsu_axi_awaddr;
440 : logic [3:0] lsu_axi_awregion;
441 : logic [7:0] lsu_axi_awlen;
442 : logic [2:0] lsu_axi_awsize;
443 : logic [1:0] lsu_axi_awburst;
444 : logic lsu_axi_awlock;
445 : logic [3:0] lsu_axi_awcache;
446 : logic [2:0] lsu_axi_awprot;
447 : logic [3:0] lsu_axi_awqos;
448 : logic lsu_axi_wvalid;
449 : logic [63:0] lsu_axi_wdata;
450 : logic [7:0] lsu_axi_wstrb;
451 : logic lsu_axi_wlast;
452 : logic lsu_axi_bready;
453 : logic lsu_axi_arvalid;
454 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;
455 : logic [31:0] lsu_axi_araddr;
456 : logic [3:0] lsu_axi_arregion;
457 : logic [7:0] lsu_axi_arlen;
458 : logic [2:0] lsu_axi_arsize;
459 : logic [1:0] lsu_axi_arburst;
460 : logic lsu_axi_arlock;
461 : logic [3:0] lsu_axi_arcache;
462 : logic [2:0] lsu_axi_arprot;
463 : logic [3:0] lsu_axi_arqos;
464 : logic lsu_axi_rready;
465 : logic ifu_axi_awvalid;
466 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;
467 : logic [31:0] ifu_axi_awaddr;
468 : logic [3:0] ifu_axi_awregion;
469 : logic [7:0] ifu_axi_awlen;
470 : logic [2:0] ifu_axi_awsize;
471 : logic [1:0] ifu_axi_awburst;
472 : logic ifu_axi_awlock;
473 : logic [3:0] ifu_axi_awcache;
474 : logic [2:0] ifu_axi_awprot;
475 : logic [3:0] ifu_axi_awqos;
476 : logic ifu_axi_wvalid;
477 : logic [63:0] ifu_axi_wdata;
478 : logic [7:0] ifu_axi_wstrb;
479 : logic ifu_axi_wlast;
480 : logic ifu_axi_bready;
481 : logic ifu_axi_arvalid;
482 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid;
483 : logic [31:0] ifu_axi_araddr;
484 : logic [3:0] ifu_axi_arregion;
485 : logic [7:0] ifu_axi_arlen;
486 : logic [2:0] ifu_axi_arsize;
487 : logic [1:0] ifu_axi_arburst;
488 : logic ifu_axi_arlock;
489 : logic [3:0] ifu_axi_arcache;
490 : logic [2:0] ifu_axi_arprot;
491 : logic [3:0] ifu_axi_arqos;
492 : logic ifu_axi_rready;
493 : logic sb_axi_awvalid;
494 : logic [pt.SB_BUS_TAG-1:0] sb_axi_awid;
495 : logic [31:0] sb_axi_awaddr;
496 : logic [3:0] sb_axi_awregion;
497 : logic [7:0] sb_axi_awlen;
498 : logic [2:0] sb_axi_awsize;
499 : logic [1:0] sb_axi_awburst;
500 : logic sb_axi_awlock;
501 : logic [3:0] sb_axi_awcache;
502 : logic [2:0] sb_axi_awprot;
503 : logic [3:0] sb_axi_awqos;
504 : logic sb_axi_wvalid;
505 : logic [63:0] sb_axi_wdata;
506 : logic [7:0] sb_axi_wstrb;
507 : logic sb_axi_wlast;
508 : logic sb_axi_bready;
509 : logic sb_axi_arvalid;
510 : logic [pt.SB_BUS_TAG-1:0] sb_axi_arid;
511 : logic [31:0] sb_axi_araddr;
512 : logic [3:0] sb_axi_arregion;
513 : logic [7:0] sb_axi_arlen;
514 : logic [2:0] sb_axi_arsize;
515 : logic [1:0] sb_axi_arburst;
516 : logic sb_axi_arlock;
517 : logic [3:0] sb_axi_arcache;
518 : logic [2:0] sb_axi_arprot;
519 : logic [3:0] sb_axi_arqos;
520 : logic sb_axi_rready;
521 : logic dma_axi_awready;
522 : logic dma_axi_wready;
523 : logic dma_axi_bvalid;
524 : logic [1:0] dma_axi_bresp;
525 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid;
526 : logic dma_axi_arready;
527 : logic dma_axi_rvalid;
528 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid;
529 : logic [63:0] dma_axi_rdata;
530 : logic [1:0] dma_axi_rresp;
531 : logic dma_axi_rlast;
532 : logic [31:0] haddr;
533 : logic [2:0] hburst;
534 : logic hmastlock;
535 : logic [3:0] hprot;
536 : logic [2:0] hsize;
537 : logic [1:0] htrans;
538 : logic hwrite;
539 : logic [31:0] lsu_haddr;
540 : logic [2:0] lsu_hburst;
541 : logic lsu_hmastlock;
542 : logic [3:0] lsu_hprot;
543 : logic [2:0] lsu_hsize;
544 : logic [1:0] lsu_htrans;
545 : logic lsu_hwrite;
546 : logic [63:0] lsu_hwdata;
547 : logic [31:0] sb_haddr;
548 : logic [2:0] sb_hburst;
549 : logic sb_hmastlock;
550 : logic [3:0] sb_hprot;
551 : logic [2:0] sb_hsize;
552 : logic [1:0] sb_htrans;
553 : logic sb_hwrite;
554 : logic [63:0] sb_hwdata;
555 : logic [63:0] dma_hrdata;
556 : logic dma_hreadyout;
557 : logic dma_hresp;
558 : logic [31:0] dmi_reg_rdata;
559 : logic iccm_ecc_single_error;
560 : logic iccm_ecc_double_error;
561 : logic dccm_ecc_single_error;
562 : logic dccm_ecc_double_error;
563 : } veer_outputs_t;
564 :
565 : // Inputs
566 : typedef struct packed {
567 : logic [31:1] rst_vec;
568 : logic nmi_int;
569 : logic [31:1] nmi_vec;
570 : logic i_cpu_halt_req;
571 : logic i_cpu_run_req;
572 : logic [31:4] core_id;
573 : logic mpc_debug_halt_req;
574 : logic mpc_debug_run_req;
575 : logic mpc_reset_run_req;
576 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;
577 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;
578 : logic [63:0] iccm_rd_data;
579 : logic [77:0] iccm_rd_data_ecc;
580 : logic [63:0] ic_rd_data;
581 : logic [70:0] ic_debug_rd_data;
582 : logic [25:0] ictag_debug_rd_data;
583 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;
584 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;
585 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit;
586 : logic ic_tag_perr;
587 : logic lsu_axi_awready;
588 : logic lsu_axi_wready;
589 : logic lsu_axi_bvalid;
590 : logic [1:0] lsu_axi_bresp;
591 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;
592 : logic lsu_axi_arready;
593 : logic lsu_axi_rvalid;
594 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;
595 : logic [63:0] lsu_axi_rdata;
596 : logic [1:0] lsu_axi_rresp;
597 : logic lsu_axi_rlast;
598 : logic ifu_axi_awready;
599 : logic ifu_axi_wready;
600 : logic ifu_axi_bvalid;
601 : logic [1:0] ifu_axi_bresp;
602 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid;
603 : logic ifu_axi_arready;
604 : logic ifu_axi_rvalid;
605 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid;
606 : logic [63:0] ifu_axi_rdata;
607 : logic [1:0] ifu_axi_rresp;
608 : logic ifu_axi_rlast;
609 : logic sb_axi_awready;
610 : logic sb_axi_wready;
611 : logic sb_axi_bvalid;
612 : logic [1:0] sb_axi_bresp;
613 : logic [pt.SB_BUS_TAG-1:0] sb_axi_bid;
614 : logic sb_axi_arready;
615 : logic sb_axi_rvalid;
616 : logic [pt.SB_BUS_TAG-1:0] sb_axi_rid;
617 : logic [63:0] sb_axi_rdata;
618 : logic [1:0] sb_axi_rresp;
619 : logic sb_axi_rlast;
620 : logic dma_axi_awvalid;
621 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid;
622 : logic [31:0] dma_axi_awaddr;
623 : logic [2:0] dma_axi_awsize;
624 : logic [2:0] dma_axi_awprot;
625 : logic [7:0] dma_axi_awlen;
626 : logic [1:0] dma_axi_awburst;
627 : logic dma_axi_wvalid;
628 : logic [63:0] dma_axi_wdata;
629 : logic [7:0] dma_axi_wstrb;
630 : logic dma_axi_wlast;
631 : logic dma_axi_bready;
632 : logic dma_axi_arvalid;
633 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid;
634 : logic [31:0] dma_axi_araddr;
635 : logic [2:0] dma_axi_arsize;
636 : logic [2:0] dma_axi_arprot;
637 : logic [7:0] dma_axi_arlen;
638 : logic [1:0] dma_axi_arburst;
639 : logic dma_axi_rready;
640 : logic [63:0] hrdata;
641 : logic hready;
642 : logic hresp;
643 : logic [63:0] lsu_hrdata;
644 : logic lsu_hready;
645 : logic lsu_hresp;
646 : logic [63:0] sb_hrdata;
647 : logic sb_hready;
648 : logic sb_hresp;
649 : logic dma_hsel;
650 : logic [31:0] dma_haddr;
651 : logic [2:0] dma_hburst;
652 : logic dma_hmastlock;
653 : logic [3:0] dma_hprot;
654 : logic [2:0] dma_hsize;
655 : logic [1:0] dma_htrans;
656 : logic dma_hwrite;
657 : logic [63:0] dma_hwdata;
658 : logic dma_hreadyin;
659 : logic lsu_bus_clk_en;
660 : logic ifu_bus_clk_en;
661 : logic dbg_bus_clk_en;
662 : logic dma_bus_clk_en;
663 : logic dmi_reg_en;
664 : logic [6:0] dmi_reg_addr;
665 : logic dmi_reg_wr_en;
666 : logic [31:0] dmi_reg_wdata;
667 : logic [pt.PIC_TOTAL_INT:1] extintsrc_req;
668 : logic timer_int;
669 : logic soft_int;
670 : logic scan_mode;
671 : } veer_inputs_t;
672 :
673 : veer_inputs_t main_core_inputs;
674 : veer_inputs_t [LockstepDelay:0] delay_input_d;
675 : veer_inputs_t shadow_core_inputs;
676 :
677 : veer_outputs_t main_core_outputs;
678 : veer_outputs_t [LockstepDelay:0] delay_output_d;
679 : veer_outputs_t delayed_main_core_outputs;
680 : veer_outputs_t shadow_core_outputs;
681 :
682 : assign shadow_core_inputs = delay_input_d[LockstepDelay];
683 : assign delayed_main_core_outputs = delay_output_d[LockstepDelay];
684 :
685 : // Capture input
686 : assign main_core_inputs.rst_vec = rst_vec;
687 : assign main_core_inputs.nmi_int = nmi_int;
688 : assign main_core_inputs.nmi_vec = nmi_vec;
689 : assign main_core_inputs.i_cpu_halt_req = i_cpu_halt_req;
690 : assign main_core_inputs.i_cpu_run_req = i_cpu_run_req;
691 : assign main_core_inputs.core_id = core_id;
692 : assign main_core_inputs.mpc_debug_halt_req = mpc_debug_halt_req;
693 : assign main_core_inputs.mpc_debug_run_req = mpc_debug_run_req;
694 : assign main_core_inputs.mpc_reset_run_req = mpc_reset_run_req;
695 : assign main_core_inputs.dccm_rd_data_lo = dccm_rd_data_lo;
696 : assign main_core_inputs.dccm_rd_data_hi = dccm_rd_data_hi;
697 : assign main_core_inputs.iccm_rd_data = iccm_rd_data;
698 : assign main_core_inputs.iccm_rd_data_ecc = iccm_rd_data_ecc;
699 : assign main_core_inputs.ic_rd_data = ic_rd_data;
700 : assign main_core_inputs.ic_debug_rd_data = ic_debug_rd_data;
701 : assign main_core_inputs.ictag_debug_rd_data = ictag_debug_rd_data;
702 : assign main_core_inputs.ic_eccerr = ic_eccerr;
703 : assign main_core_inputs.ic_parerr = ic_parerr;
704 : assign main_core_inputs.ic_rd_hit = ic_rd_hit;
705 : assign main_core_inputs.ic_tag_perr = ic_tag_perr;
706 : assign main_core_inputs.lsu_axi_awready = lsu_axi_awready;
707 : assign main_core_inputs.lsu_axi_wready = lsu_axi_wready;
708 : assign main_core_inputs.lsu_axi_bvalid = lsu_axi_bvalid;
709 : assign main_core_inputs.lsu_axi_bresp = lsu_axi_bresp;
710 : assign main_core_inputs.lsu_axi_bid = lsu_axi_bid;
711 : assign main_core_inputs.lsu_axi_arready = lsu_axi_arready;
712 : assign main_core_inputs.lsu_axi_rvalid = lsu_axi_rvalid;
713 : assign main_core_inputs.lsu_axi_rid = lsu_axi_rid;
714 : assign main_core_inputs.lsu_axi_rdata = lsu_axi_rdata;
715 : assign main_core_inputs.lsu_axi_rresp = lsu_axi_rresp;
716 : assign main_core_inputs.lsu_axi_rlast = lsu_axi_rlast;
717 : assign main_core_inputs.ifu_axi_awready = ifu_axi_awready;
718 : assign main_core_inputs.ifu_axi_wready = ifu_axi_wready;
719 : assign main_core_inputs.ifu_axi_bvalid = ifu_axi_bvalid;
720 : assign main_core_inputs.ifu_axi_bresp = ifu_axi_bresp;
721 : assign main_core_inputs.ifu_axi_bid = ifu_axi_bid;
722 : assign main_core_inputs.ifu_axi_arready = ifu_axi_arready;
723 : assign main_core_inputs.ifu_axi_rvalid = ifu_axi_rvalid;
724 : assign main_core_inputs.ifu_axi_rid = ifu_axi_rid;
725 : assign main_core_inputs.ifu_axi_rdata = ifu_axi_rdata;
726 : assign main_core_inputs.ifu_axi_rresp = ifu_axi_rresp;
727 : assign main_core_inputs.ifu_axi_rlast = ifu_axi_rlast;
728 : assign main_core_inputs.sb_axi_awready = sb_axi_awready;
729 : assign main_core_inputs.sb_axi_wready = sb_axi_wready;
730 : assign main_core_inputs.sb_axi_bvalid = sb_axi_bvalid;
731 : assign main_core_inputs.sb_axi_bresp = sb_axi_bresp;
732 : assign main_core_inputs.sb_axi_bid = sb_axi_bid;
733 : assign main_core_inputs.sb_axi_arready = sb_axi_arready;
734 : assign main_core_inputs.sb_axi_rvalid = sb_axi_rvalid;
735 : assign main_core_inputs.sb_axi_rid = sb_axi_rid;
736 : assign main_core_inputs.sb_axi_rdata = sb_axi_rdata;
737 : assign main_core_inputs.sb_axi_rresp = sb_axi_rresp;
738 : assign main_core_inputs.sb_axi_rlast = sb_axi_rlast;
739 : assign main_core_inputs.dma_axi_awvalid = dma_axi_awvalid;
740 : assign main_core_inputs.dma_axi_awid = dma_axi_awid;
741 : assign main_core_inputs.dma_axi_awaddr = dma_axi_awaddr;
742 : assign main_core_inputs.dma_axi_awsize = dma_axi_awsize;
743 : assign main_core_inputs.dma_axi_awprot = dma_axi_awprot;
744 : assign main_core_inputs.dma_axi_awlen = dma_axi_awlen;
745 : assign main_core_inputs.dma_axi_awburst = dma_axi_awburst;
746 : assign main_core_inputs.dma_axi_wvalid = dma_axi_wvalid;
747 : assign main_core_inputs.dma_axi_wdata = dma_axi_wdata;
748 : assign main_core_inputs.dma_axi_wstrb = dma_axi_wstrb;
749 : assign main_core_inputs.dma_axi_wlast = dma_axi_wlast;
750 : assign main_core_inputs.dma_axi_bready = dma_axi_bready;
751 : assign main_core_inputs.dma_axi_arvalid = dma_axi_arvalid;
752 : assign main_core_inputs.dma_axi_arid = dma_axi_arid;
753 : assign main_core_inputs.dma_axi_araddr = dma_axi_araddr;
754 : assign main_core_inputs.dma_axi_arsize = dma_axi_arsize;
755 : assign main_core_inputs.dma_axi_arprot = dma_axi_arprot;
756 : assign main_core_inputs.dma_axi_arlen = dma_axi_arlen;
757 : assign main_core_inputs.dma_axi_arburst = dma_axi_arburst;
758 : assign main_core_inputs.dma_axi_rready = dma_axi_rready;
759 : assign main_core_inputs.hrdata = hrdata;
760 : assign main_core_inputs.hready = hready;
761 : assign main_core_inputs.hresp = hresp;
762 : assign main_core_inputs.lsu_hrdata = lsu_hrdata;
763 : assign main_core_inputs.lsu_hready = lsu_hready;
764 : assign main_core_inputs.lsu_hresp = lsu_hresp;
765 : assign main_core_inputs.sb_hrdata = sb_hrdata;
766 : assign main_core_inputs.sb_hready = sb_hready;
767 : assign main_core_inputs.sb_hresp = sb_hresp;
768 : assign main_core_inputs.dma_hsel = dma_hsel;
769 : assign main_core_inputs.dma_haddr = dma_haddr;
770 : assign main_core_inputs.dma_hburst = dma_hburst;
771 : assign main_core_inputs.dma_hmastlock = dma_hmastlock;
772 : assign main_core_inputs.dma_hprot = dma_hprot;
773 : assign main_core_inputs.dma_hsize = dma_hsize;
774 : assign main_core_inputs.dma_htrans = dma_htrans;
775 : assign main_core_inputs.dma_hwrite = dma_hwrite;
776 : assign main_core_inputs.dma_hwdata = dma_hwdata;
777 : assign main_core_inputs.dma_hreadyin = dma_hreadyin;
778 : assign main_core_inputs.lsu_bus_clk_en = lsu_bus_clk_en;
779 : assign main_core_inputs.ifu_bus_clk_en = ifu_bus_clk_en;
780 : assign main_core_inputs.dbg_bus_clk_en = dbg_bus_clk_en;
781 : assign main_core_inputs.dma_bus_clk_en = dma_bus_clk_en;
782 : assign main_core_inputs.dmi_reg_en = dmi_reg_en;
783 : assign main_core_inputs.dmi_reg_addr = dmi_reg_addr;
784 : assign main_core_inputs.dmi_reg_wr_en = dmi_reg_wr_en;
785 : assign main_core_inputs.dmi_reg_wdata = dmi_reg_wdata;
786 : assign main_core_inputs.extintsrc_req = extintsrc_req;
787 : assign main_core_inputs.timer_int = timer_int;
788 : assign main_core_inputs.soft_int = soft_int;
789 : assign main_core_inputs.scan_mode = scan_mode;
790 :
791 : // Capture output
792 : assign main_core_outputs.core_rst_l = core_rst_l;
793 : assign main_core_outputs.trace_rv_i_insn_ip = trace_rv_i_insn_ip;
794 : assign main_core_outputs.trace_rv_i_address_ip = trace_rv_i_address_ip;
795 : assign main_core_outputs.trace_rv_i_valid_ip = trace_rv_i_valid_ip;
796 : assign main_core_outputs.trace_rv_i_exception_ip = trace_rv_i_exception_ip;
797 : assign main_core_outputs.trace_rv_i_ecause_ip = trace_rv_i_ecause_ip;
798 : assign main_core_outputs.trace_rv_i_interrupt_ip = trace_rv_i_interrupt_ip;
799 : assign main_core_outputs.trace_rv_i_tval_ip = trace_rv_i_tval_ip;
800 : assign main_core_outputs.dccm_clk_override = dccm_clk_override;
801 : assign main_core_outputs.icm_clk_override = icm_clk_override;
802 : assign main_core_outputs.dec_tlu_core_ecc_disable = dec_tlu_core_ecc_disable;
803 : assign main_core_outputs.o_cpu_halt_ack = o_cpu_halt_ack;
804 : assign main_core_outputs.o_cpu_halt_status = o_cpu_halt_status;
805 : assign main_core_outputs.o_cpu_run_ack = o_cpu_run_ack;
806 : assign main_core_outputs.o_debug_mode_status = o_debug_mode_status;
807 : assign main_core_outputs.mpc_debug_halt_ack = mpc_debug_halt_ack;
808 : assign main_core_outputs.mpc_debug_run_ack = mpc_debug_run_ack;
809 : assign main_core_outputs.debug_brkpt_status = debug_brkpt_status;
810 : assign main_core_outputs.dec_tlu_perfcnt0 = dec_tlu_perfcnt0;
811 : assign main_core_outputs.dec_tlu_perfcnt1 = dec_tlu_perfcnt1;
812 : assign main_core_outputs.dec_tlu_perfcnt2 = dec_tlu_perfcnt2;
813 : assign main_core_outputs.dec_tlu_perfcnt3 = dec_tlu_perfcnt3;
814 : assign main_core_outputs.dccm_wren = dccm_wren;
815 : assign main_core_outputs.dccm_rden = dccm_rden;
816 : assign main_core_outputs.dccm_wr_addr_lo = dccm_wr_addr_lo;
817 : assign main_core_outputs.dccm_wr_addr_hi = dccm_wr_addr_hi;
818 : assign main_core_outputs.dccm_rd_addr_lo = dccm_rd_addr_lo;
819 : assign main_core_outputs.dccm_rd_addr_hi = dccm_rd_addr_hi;
820 : assign main_core_outputs.dccm_wr_data_lo = dccm_wr_data_lo;
821 : assign main_core_outputs.dccm_wr_data_hi = dccm_wr_data_hi;
822 : assign main_core_outputs.iccm_rw_addr = iccm_rw_addr;
823 : assign main_core_outputs.iccm_wren = iccm_wren;
824 : assign main_core_outputs.iccm_rden = iccm_rden;
825 : assign main_core_outputs.iccm_wr_size = iccm_wr_size;
826 : assign main_core_outputs.iccm_wr_data = iccm_wr_data;
827 : assign main_core_outputs.iccm_buf_correct_ecc = iccm_buf_correct_ecc;
828 : assign main_core_outputs.iccm_correction_state = iccm_correction_state;
829 : assign main_core_outputs.ic_rw_addr = ic_rw_addr;
830 : assign main_core_outputs.ic_tag_valid = ic_tag_valid;
831 : assign main_core_outputs.ic_wr_en = ic_wr_en;
832 : assign main_core_outputs.ic_rd_en = ic_rd_en;
833 : assign main_core_outputs.ic_wr_data = ic_wr_data;
834 : assign main_core_outputs.ic_debug_wr_data = ic_debug_wr_data;
835 : assign main_core_outputs.ic_premux_data = ic_premux_data;
836 : assign main_core_outputs.ic_sel_premux_data = ic_sel_premux_data;
837 : assign main_core_outputs.ic_debug_addr = ic_debug_addr;
838 : assign main_core_outputs.ic_debug_rd_en = ic_debug_rd_en;
839 : assign main_core_outputs.ic_debug_wr_en = ic_debug_wr_en;
840 : assign main_core_outputs.ic_debug_tag_array = ic_debug_tag_array;
841 : assign main_core_outputs.ic_debug_way = ic_debug_way;
842 : assign main_core_outputs.lsu_axi_awvalid = lsu_axi_awvalid;
843 : assign main_core_outputs.lsu_axi_awid = lsu_axi_awid;
844 : assign main_core_outputs.lsu_axi_awaddr = lsu_axi_awaddr;
845 : assign main_core_outputs.lsu_axi_awregion = lsu_axi_awregion;
846 : assign main_core_outputs.lsu_axi_awlen = lsu_axi_awlen;
847 : assign main_core_outputs.lsu_axi_awsize = lsu_axi_awsize;
848 : assign main_core_outputs.lsu_axi_awburst = lsu_axi_awburst;
849 : assign main_core_outputs.lsu_axi_awlock = lsu_axi_awlock;
850 : assign main_core_outputs.lsu_axi_awcache = lsu_axi_awcache;
851 : assign main_core_outputs.lsu_axi_awprot = lsu_axi_awprot;
852 : assign main_core_outputs.lsu_axi_awqos = lsu_axi_awqos;
853 : assign main_core_outputs.lsu_axi_wvalid = lsu_axi_wvalid;
854 : assign main_core_outputs.lsu_axi_wdata = lsu_axi_wdata;
855 : assign main_core_outputs.lsu_axi_wstrb = lsu_axi_wstrb;
856 : assign main_core_outputs.lsu_axi_wlast = lsu_axi_wlast;
857 : assign main_core_outputs.lsu_axi_bready = lsu_axi_bready;
858 : assign main_core_outputs.lsu_axi_arvalid = lsu_axi_arvalid;
859 : assign main_core_outputs.lsu_axi_arid = lsu_axi_arid;
860 : assign main_core_outputs.lsu_axi_araddr = lsu_axi_araddr;
861 : assign main_core_outputs.lsu_axi_arregion = lsu_axi_arregion;
862 : assign main_core_outputs.lsu_axi_arlen = lsu_axi_arlen;
863 : assign main_core_outputs.lsu_axi_arsize = lsu_axi_arsize;
864 : assign main_core_outputs.lsu_axi_arburst = lsu_axi_arburst;
865 : assign main_core_outputs.lsu_axi_arlock = lsu_axi_arlock;
866 : assign main_core_outputs.lsu_axi_arcache = lsu_axi_arcache;
867 : assign main_core_outputs.lsu_axi_arprot = lsu_axi_arprot;
868 : assign main_core_outputs.lsu_axi_arqos = lsu_axi_arqos;
869 : assign main_core_outputs.lsu_axi_rready = lsu_axi_rready;
870 : assign main_core_outputs.ifu_axi_awvalid = ifu_axi_awvalid;
871 : assign main_core_outputs.ifu_axi_awid = ifu_axi_awid;
872 : assign main_core_outputs.ifu_axi_awaddr = ifu_axi_awaddr;
873 : assign main_core_outputs.ifu_axi_awregion = ifu_axi_awregion;
874 : assign main_core_outputs.ifu_axi_awlen = ifu_axi_awlen;
875 : assign main_core_outputs.ifu_axi_awsize = ifu_axi_awsize;
876 : assign main_core_outputs.ifu_axi_awburst = ifu_axi_awburst;
877 : assign main_core_outputs.ifu_axi_awlock = ifu_axi_awlock;
878 : assign main_core_outputs.ifu_axi_awcache = ifu_axi_awcache;
879 : assign main_core_outputs.ifu_axi_awprot = ifu_axi_awprot;
880 : assign main_core_outputs.ifu_axi_awqos = ifu_axi_awqos;
881 : assign main_core_outputs.ifu_axi_wvalid = ifu_axi_wvalid;
882 : assign main_core_outputs.ifu_axi_wdata = ifu_axi_wdata;
883 : assign main_core_outputs.ifu_axi_wstrb = ifu_axi_wstrb;
884 : assign main_core_outputs.ifu_axi_wlast = ifu_axi_wlast;
885 : assign main_core_outputs.ifu_axi_bready = ifu_axi_bready;
886 : assign main_core_outputs.ifu_axi_arvalid = ifu_axi_arvalid;
887 : assign main_core_outputs.ifu_axi_arid = ifu_axi_arid;
888 : assign main_core_outputs.ifu_axi_araddr = ifu_axi_araddr;
889 : assign main_core_outputs.ifu_axi_arregion = ifu_axi_arregion;
890 : assign main_core_outputs.ifu_axi_arlen = ifu_axi_arlen;
891 : assign main_core_outputs.ifu_axi_arsize = ifu_axi_arsize;
892 : assign main_core_outputs.ifu_axi_arburst = ifu_axi_arburst;
893 : assign main_core_outputs.ifu_axi_arlock = ifu_axi_arlock;
894 : assign main_core_outputs.ifu_axi_arcache = ifu_axi_arcache;
895 : assign main_core_outputs.ifu_axi_arprot = ifu_axi_arprot;
896 : assign main_core_outputs.ifu_axi_arqos = ifu_axi_arqos;
897 : assign main_core_outputs.ifu_axi_rready = ifu_axi_rready;
898 : assign main_core_outputs.sb_axi_awvalid = sb_axi_awvalid;
899 : assign main_core_outputs.sb_axi_awid = sb_axi_awid;
900 : assign main_core_outputs.sb_axi_awaddr = sb_axi_awaddr;
901 : assign main_core_outputs.sb_axi_awregion = sb_axi_awregion;
902 : assign main_core_outputs.sb_axi_awlen = sb_axi_awlen;
903 : assign main_core_outputs.sb_axi_awsize = sb_axi_awsize;
904 : assign main_core_outputs.sb_axi_awburst = sb_axi_awburst;
905 : assign main_core_outputs.sb_axi_awlock = sb_axi_awlock;
906 : assign main_core_outputs.sb_axi_awcache = sb_axi_awcache;
907 : assign main_core_outputs.sb_axi_awprot = sb_axi_awprot;
908 : assign main_core_outputs.sb_axi_awqos = sb_axi_awqos;
909 : assign main_core_outputs.sb_axi_wvalid = sb_axi_wvalid;
910 : assign main_core_outputs.sb_axi_wdata = sb_axi_wdata;
911 : assign main_core_outputs.sb_axi_wstrb = sb_axi_wstrb;
912 : assign main_core_outputs.sb_axi_wlast = sb_axi_wlast;
913 : assign main_core_outputs.sb_axi_bready = sb_axi_bready;
914 : assign main_core_outputs.sb_axi_arvalid = sb_axi_arvalid;
915 : assign main_core_outputs.sb_axi_arid = sb_axi_arid;
916 : assign main_core_outputs.sb_axi_araddr = sb_axi_araddr;
917 : assign main_core_outputs.sb_axi_arregion = sb_axi_arregion;
918 : assign main_core_outputs.sb_axi_arlen = sb_axi_arlen;
919 : assign main_core_outputs.sb_axi_arsize = sb_axi_arsize;
920 : assign main_core_outputs.sb_axi_arburst = sb_axi_arburst;
921 : assign main_core_outputs.sb_axi_arlock = sb_axi_arlock;
922 : assign main_core_outputs.sb_axi_arcache = sb_axi_arcache;
923 : assign main_core_outputs.sb_axi_arprot = sb_axi_arprot;
924 : assign main_core_outputs.sb_axi_arqos = sb_axi_arqos;
925 : assign main_core_outputs.sb_axi_rready = sb_axi_rready;
926 : assign main_core_outputs.dma_axi_awready = dma_axi_awready;
927 : assign main_core_outputs.dma_axi_wready = dma_axi_wready;
928 : assign main_core_outputs.dma_axi_bvalid = dma_axi_bvalid;
929 : assign main_core_outputs.dma_axi_bresp = dma_axi_bresp;
930 : assign main_core_outputs.dma_axi_bid = dma_axi_bid;
931 : assign main_core_outputs.dma_axi_arready = dma_axi_arready;
932 : assign main_core_outputs.dma_axi_rvalid = dma_axi_rvalid;
933 : assign main_core_outputs.dma_axi_rid = dma_axi_rid;
934 : assign main_core_outputs.dma_axi_rdata = dma_axi_rdata;
935 : assign main_core_outputs.dma_axi_rresp = dma_axi_rresp;
936 : assign main_core_outputs.dma_axi_rlast = dma_axi_rlast;
937 : assign main_core_outputs.haddr = haddr;
938 : assign main_core_outputs.hburst = hburst;
939 : assign main_core_outputs.hmastlock = hmastlock;
940 : assign main_core_outputs.hprot = hprot;
941 : assign main_core_outputs.hsize = hsize;
942 : assign main_core_outputs.htrans = htrans;
943 : assign main_core_outputs.hwrite = hwrite;
944 : assign main_core_outputs.lsu_haddr = lsu_haddr;
945 : assign main_core_outputs.lsu_hburst = lsu_hburst;
946 : assign main_core_outputs.lsu_hmastlock = lsu_hmastlock;
947 : assign main_core_outputs.lsu_hprot = lsu_hprot;
948 : assign main_core_outputs.lsu_hsize = lsu_hsize;
949 : assign main_core_outputs.lsu_htrans = lsu_htrans;
950 : assign main_core_outputs.lsu_hwrite = lsu_hwrite;
951 : assign main_core_outputs.lsu_hwdata = lsu_hwdata;
952 : assign main_core_outputs.sb_haddr = sb_haddr;
953 : assign main_core_outputs.sb_hburst = sb_hburst;
954 : assign main_core_outputs.sb_hmastlock = sb_hmastlock;
955 : assign main_core_outputs.sb_hprot = sb_hprot;
956 : assign main_core_outputs.sb_hsize = sb_hsize;
957 : assign main_core_outputs.sb_htrans = sb_htrans;
958 : assign main_core_outputs.sb_hwrite = sb_hwrite;
959 : assign main_core_outputs.sb_hwdata = sb_hwdata;
960 : assign main_core_outputs.dma_hrdata = dma_hrdata;
961 : assign main_core_outputs.dma_hreadyout = dma_hreadyout;
962 : assign main_core_outputs.dma_hresp = dma_hresp;
963 : assign main_core_outputs.dmi_reg_rdata = dmi_reg_rdata;
964 : assign main_core_outputs.iccm_ecc_single_error = iccm_ecc_single_error;
965 : assign main_core_outputs.iccm_ecc_double_error = iccm_ecc_double_error;
966 : assign main_core_outputs.dccm_ecc_single_error = dccm_ecc_single_error;
967 : assign main_core_outputs.dccm_ecc_double_error = dccm_ecc_double_error;
968 :
969 : // Shadow core enters reset immediately with main core but gets out of reset
970 : // after the delay
971 3 : logic [LockstepDelay:0] rst_shadow_sr, rst_dbg_shadow_sr;
972 3 : logic rst_shadow, rst_dbg_shadow;
973 : assign rst_shadow = &rst_shadow_sr;
974 : assign rst_dbg_shadow = &rst_dbg_shadow_sr;
975 :
976 47 : always_ff @(posedge clk or negedge rst_l) begin
977 5 : if (!rst_l) begin
978 5 : rst_shadow_sr <= '0;
979 42 : end else begin
980 42 : rst_shadow_sr <= (rst_shadow_sr << 1) + 1;
981 : end
982 : end
983 :
984 47 : always_ff @(posedge clk or negedge dbg_rst_l) begin
985 5 : if (!dbg_rst_l) begin
986 5 : rst_dbg_shadow_sr <= '0;
987 42 : end else begin
988 42 : rst_dbg_shadow_sr <= (rst_dbg_shadow_sr << 1) + 1;
989 : end
990 : end
991 :
992 : // Delay the inputs and outputs
993 47 : always_ff @(posedge clk or negedge rst_l) begin
994 5 : if (~rst_l) begin
995 5 : delay_input_d[0] <= veer_inputs_t'(0);
996 5 : delay_output_d[0] <= veer_outputs_t'(0);
997 42 : end else begin
998 42 : delay_input_d[0] <= main_core_inputs;
999 42 : delay_output_d[0] <= main_core_outputs;
1000 : end
1001 : end
1002 15 : for (genvar i = 0; i < LockstepDelay; i++) begin
1003 141 : always_ff @(posedge clk or negedge rst_l) begin
1004 15 : if (!rst_l) begin
1005 15 : delay_input_d[i+1] <= veer_inputs_t'(0);
1006 15 : delay_output_d[i+1] <= veer_outputs_t'(0);
1007 126 : end else begin
1008 126 : delay_input_d[i+1] <= delay_input_d[i];
1009 126 : delay_output_d[i+1] <= delay_output_d[i];
1010 : end
1011 : end
1012 : end
1013 :
1014 : `ifdef RV_LOCKSTEP_REGFILE_ENABLE
1015 : el2_regfile_if shadow_core_regfile ();
1016 :
1017 : el2_regfile_if delayed_main_core_regfile[LockstepDelay:0] ();
1018 :
1019 47 : always_ff @(posedge clk or negedge rst_l) begin
1020 5 : if (!rst_l) begin
1021 5 : delayed_main_core_regfile[0].gpr <= '0;
1022 5 : delayed_main_core_regfile[0].tlu <= '0;
1023 42 : end else begin
1024 42 : delayed_main_core_regfile[0].gpr <= main_core_regfile.gpr;
1025 42 : delayed_main_core_regfile[0].tlu <= main_core_regfile.tlu;
1026 : end
1027 : end
1028 : for (genvar i = 0; i < LockstepDelay; i++) begin
1029 141 : always_ff @(posedge clk or negedge rst_l) begin
1030 15 : if (!rst_l) begin
1031 15 : delayed_main_core_regfile[i+1].gpr <= '0;
1032 15 : delayed_main_core_regfile[i+1].tlu <= '0;
1033 126 : end else begin
1034 126 : delayed_main_core_regfile[i+1].gpr <= delayed_main_core_regfile[i].gpr;
1035 126 : delayed_main_core_regfile[i+1].tlu <= delayed_main_core_regfile[i].tlu;
1036 : end
1037 : end
1038 : end
1039 : `endif
1040 :
1041 91 : logic unused_active_l2clk, unused_free_l2clk;
1042 :
1043 : // Instantiate the el2_veer core
1044 : el2_veer #(
1045 : .pt(pt)
1046 : ) xshadow_core (
1047 : `ifdef RV_LOCKSTEP_REGFILE_ENABLE
1048 : .regfile(shadow_core_regfile.veer_rf_src),
1049 : `endif
1050 : .clk(clk),
1051 : .rst_l(rst_shadow),
1052 : .dbg_rst_l(rst_dbg_shadow),
1053 : .rst_vec(shadow_core_inputs.rst_vec),
1054 : .nmi_int(shadow_core_inputs.nmi_int),
1055 : .nmi_vec(shadow_core_inputs.nmi_vec),
1056 : .core_rst_l(shadow_core_outputs.core_rst_l),
1057 :
1058 : .active_l2clk(unused_active_l2clk),
1059 : .free_l2clk (unused_free_l2clk),
1060 :
1061 : .trace_rv_i_insn_ip(shadow_core_outputs.trace_rv_i_insn_ip),
1062 : .trace_rv_i_address_ip(shadow_core_outputs.trace_rv_i_address_ip),
1063 : .trace_rv_i_valid_ip(shadow_core_outputs.trace_rv_i_valid_ip),
1064 : .trace_rv_i_exception_ip(shadow_core_outputs.trace_rv_i_exception_ip),
1065 : .trace_rv_i_ecause_ip(shadow_core_outputs.trace_rv_i_ecause_ip),
1066 : .trace_rv_i_interrupt_ip(shadow_core_outputs.trace_rv_i_interrupt_ip),
1067 : .trace_rv_i_tval_ip(shadow_core_outputs.trace_rv_i_tval_ip),
1068 :
1069 : .dccm_clk_override(shadow_core_outputs.dccm_clk_override),
1070 : .icm_clk_override(shadow_core_outputs.icm_clk_override),
1071 : .dec_tlu_core_ecc_disable(shadow_core_outputs.dec_tlu_core_ecc_disable),
1072 :
1073 : .i_cpu_halt_req(shadow_core_inputs.i_cpu_halt_req),
1074 : .i_cpu_run_req(shadow_core_inputs.i_cpu_run_req),
1075 : .o_cpu_halt_ack(shadow_core_outputs.o_cpu_halt_ack),
1076 : .o_cpu_halt_status(shadow_core_outputs.o_cpu_halt_status),
1077 : .o_cpu_run_ack(shadow_core_outputs.o_cpu_run_ack),
1078 : .o_debug_mode_status(shadow_core_outputs.o_debug_mode_status),
1079 :
1080 : .core_id(core_id),
1081 :
1082 : .mpc_debug_halt_req(shadow_core_inputs.mpc_debug_halt_req),
1083 : .mpc_debug_run_req (shadow_core_inputs.mpc_debug_run_req),
1084 : .mpc_reset_run_req (shadow_core_inputs.mpc_reset_run_req),
1085 : .mpc_debug_halt_ack(shadow_core_outputs.mpc_debug_halt_ack),
1086 : .mpc_debug_run_ack (shadow_core_outputs.mpc_debug_run_ack),
1087 : .debug_brkpt_status(shadow_core_outputs.debug_brkpt_status),
1088 :
1089 : .dec_tlu_perfcnt0(shadow_core_outputs.dec_tlu_perfcnt0),
1090 : .dec_tlu_perfcnt1(shadow_core_outputs.dec_tlu_perfcnt1),
1091 : .dec_tlu_perfcnt2(shadow_core_outputs.dec_tlu_perfcnt2),
1092 : .dec_tlu_perfcnt3(shadow_core_outputs.dec_tlu_perfcnt3),
1093 :
1094 : .dccm_wren(shadow_core_outputs.dccm_wren),
1095 : .dccm_rden(shadow_core_outputs.dccm_rden),
1096 : .dccm_wr_addr_lo(shadow_core_outputs.dccm_wr_addr_lo),
1097 : .dccm_wr_addr_hi(shadow_core_outputs.dccm_wr_addr_hi),
1098 : .dccm_rd_addr_lo(shadow_core_outputs.dccm_rd_addr_lo),
1099 : .dccm_rd_addr_hi(shadow_core_outputs.dccm_rd_addr_hi),
1100 : .dccm_wr_data_lo(shadow_core_outputs.dccm_wr_data_lo),
1101 : .dccm_wr_data_hi(shadow_core_outputs.dccm_wr_data_hi),
1102 : .dccm_rd_data_lo(shadow_core_inputs.dccm_rd_data_lo),
1103 : .dccm_rd_data_hi(shadow_core_inputs.dccm_rd_data_hi),
1104 :
1105 : .iccm_rw_addr(shadow_core_outputs.iccm_rw_addr),
1106 : .iccm_wren(shadow_core_outputs.iccm_wren),
1107 : .iccm_rden(shadow_core_outputs.iccm_rden),
1108 : .iccm_wr_size(shadow_core_outputs.iccm_wr_size),
1109 : .iccm_wr_data(shadow_core_outputs.iccm_wr_data),
1110 : .iccm_buf_correct_ecc(shadow_core_outputs.iccm_buf_correct_ecc),
1111 : .iccm_correction_state(shadow_core_outputs.iccm_correction_state),
1112 : .iccm_rd_data(shadow_core_inputs.iccm_rd_data),
1113 : .iccm_rd_data_ecc(shadow_core_inputs.iccm_rd_data_ecc),
1114 :
1115 : .ic_rw_addr(shadow_core_outputs.ic_rw_addr),
1116 : .ic_tag_valid(shadow_core_outputs.ic_tag_valid),
1117 : .ic_wr_en(shadow_core_outputs.ic_wr_en),
1118 : .ic_rd_en(shadow_core_outputs.ic_rd_en),
1119 :
1120 : .ic_wr_data(shadow_core_outputs.ic_wr_data),
1121 : .ic_rd_data(shadow_core_inputs.ic_rd_data),
1122 : .ic_debug_rd_data(shadow_core_inputs.ic_debug_rd_data),
1123 : .ictag_debug_rd_data(shadow_core_inputs.ictag_debug_rd_data),
1124 : .ic_debug_wr_data(shadow_core_outputs.ic_debug_wr_data),
1125 :
1126 : .ic_eccerr(shadow_core_inputs.ic_eccerr),
1127 : .ic_parerr(shadow_core_inputs.ic_parerr),
1128 : .ic_premux_data(shadow_core_outputs.ic_premux_data),
1129 : .ic_sel_premux_data(shadow_core_outputs.ic_sel_premux_data),
1130 :
1131 : .ic_debug_addr(shadow_core_outputs.ic_debug_addr),
1132 : .ic_debug_rd_en(shadow_core_outputs.ic_debug_rd_en),
1133 : .ic_debug_wr_en(shadow_core_outputs.ic_debug_wr_en),
1134 : .ic_debug_tag_array(shadow_core_outputs.ic_debug_tag_array),
1135 : .ic_debug_way(shadow_core_outputs.ic_debug_way),
1136 :
1137 : .ic_rd_hit (shadow_core_inputs.ic_rd_hit),
1138 : .ic_tag_perr(shadow_core_inputs.ic_tag_perr),
1139 :
1140 : .lsu_axi_awvalid(shadow_core_outputs.lsu_axi_awvalid),
1141 : .lsu_axi_awready(shadow_core_inputs.lsu_axi_awready),
1142 : .lsu_axi_awid(shadow_core_outputs.lsu_axi_awid),
1143 : .lsu_axi_awaddr(shadow_core_outputs.lsu_axi_awaddr),
1144 : .lsu_axi_awregion(shadow_core_outputs.lsu_axi_awregion),
1145 : .lsu_axi_awlen(shadow_core_outputs.lsu_axi_awlen),
1146 : .lsu_axi_awsize(shadow_core_outputs.lsu_axi_awsize),
1147 : .lsu_axi_awburst(shadow_core_outputs.lsu_axi_awburst),
1148 : .lsu_axi_awlock(shadow_core_outputs.lsu_axi_awlock),
1149 : .lsu_axi_awcache(shadow_core_outputs.lsu_axi_awcache),
1150 : .lsu_axi_awprot(shadow_core_outputs.lsu_axi_awprot),
1151 : .lsu_axi_awqos(shadow_core_outputs.lsu_axi_awqos),
1152 : .lsu_axi_wvalid(shadow_core_outputs.lsu_axi_wvalid),
1153 : .lsu_axi_wready(shadow_core_inputs.lsu_axi_wready),
1154 : .lsu_axi_wdata(shadow_core_outputs.lsu_axi_wdata),
1155 : .lsu_axi_wstrb(shadow_core_outputs.lsu_axi_wstrb),
1156 : .lsu_axi_wlast(shadow_core_outputs.lsu_axi_wlast),
1157 : .lsu_axi_bvalid(shadow_core_inputs.lsu_axi_bvalid),
1158 : .lsu_axi_bready(shadow_core_outputs.lsu_axi_bready),
1159 : .lsu_axi_bresp(shadow_core_inputs.lsu_axi_bresp),
1160 : .lsu_axi_bid(shadow_core_inputs.lsu_axi_bid),
1161 : .lsu_axi_arvalid(shadow_core_outputs.lsu_axi_arvalid),
1162 : .lsu_axi_arready(shadow_core_inputs.lsu_axi_arready),
1163 : .lsu_axi_arid(shadow_core_outputs.lsu_axi_arid),
1164 : .lsu_axi_araddr(shadow_core_outputs.lsu_axi_araddr),
1165 : .lsu_axi_arregion(shadow_core_outputs.lsu_axi_arregion),
1166 : .lsu_axi_arlen(shadow_core_outputs.lsu_axi_arlen),
1167 : .lsu_axi_arsize(shadow_core_outputs.lsu_axi_arsize),
1168 : .lsu_axi_arburst(shadow_core_outputs.lsu_axi_arburst),
1169 : .lsu_axi_arlock(shadow_core_outputs.lsu_axi_arlock),
1170 : .lsu_axi_arcache(shadow_core_outputs.lsu_axi_arcache),
1171 : .lsu_axi_arprot(shadow_core_outputs.lsu_axi_arprot),
1172 : .lsu_axi_arqos(shadow_core_outputs.lsu_axi_arqos),
1173 : .lsu_axi_rvalid(shadow_core_inputs.lsu_axi_rvalid),
1174 : .lsu_axi_rready(shadow_core_outputs.lsu_axi_rready),
1175 : .lsu_axi_rid(shadow_core_inputs.lsu_axi_rid),
1176 : .lsu_axi_rdata(shadow_core_inputs.lsu_axi_rdata),
1177 : .lsu_axi_rresp(shadow_core_inputs.lsu_axi_rresp),
1178 : .lsu_axi_rlast(shadow_core_inputs.lsu_axi_rlast),
1179 :
1180 : .ifu_axi_awvalid(shadow_core_outputs.ifu_axi_awvalid),
1181 : .ifu_axi_awready(shadow_core_inputs.ifu_axi_awready),
1182 : .ifu_axi_awid(shadow_core_outputs.ifu_axi_awid),
1183 : .ifu_axi_awaddr(shadow_core_outputs.ifu_axi_awaddr),
1184 : .ifu_axi_awregion(shadow_core_outputs.ifu_axi_awregion),
1185 : .ifu_axi_awlen(shadow_core_outputs.ifu_axi_awlen),
1186 : .ifu_axi_awsize(shadow_core_outputs.ifu_axi_awsize),
1187 : .ifu_axi_awburst(shadow_core_outputs.ifu_axi_awburst),
1188 : .ifu_axi_awlock(shadow_core_outputs.ifu_axi_awlock),
1189 : .ifu_axi_awcache(shadow_core_outputs.ifu_axi_awcache),
1190 : .ifu_axi_awprot(shadow_core_outputs.ifu_axi_awprot),
1191 : .ifu_axi_awqos(shadow_core_outputs.ifu_axi_awqos),
1192 : .ifu_axi_wvalid(shadow_core_outputs.ifu_axi_wvalid),
1193 : .ifu_axi_wready(shadow_core_inputs.ifu_axi_wready),
1194 : .ifu_axi_wdata(shadow_core_outputs.ifu_axi_wdata),
1195 : .ifu_axi_wstrb(shadow_core_outputs.ifu_axi_wstrb),
1196 : .ifu_axi_wlast(shadow_core_outputs.ifu_axi_wlast),
1197 : .ifu_axi_bvalid(shadow_core_inputs.ifu_axi_bvalid),
1198 : .ifu_axi_bready(shadow_core_outputs.ifu_axi_bready),
1199 : .ifu_axi_bresp(shadow_core_inputs.ifu_axi_bresp),
1200 : .ifu_axi_bid(shadow_core_inputs.ifu_axi_bid),
1201 : .ifu_axi_arvalid(shadow_core_outputs.ifu_axi_arvalid),
1202 : .ifu_axi_arready(shadow_core_inputs.ifu_axi_arready),
1203 : .ifu_axi_arid(shadow_core_outputs.ifu_axi_arid),
1204 : .ifu_axi_araddr(shadow_core_outputs.ifu_axi_araddr),
1205 : .ifu_axi_arregion(shadow_core_outputs.ifu_axi_arregion),
1206 : .ifu_axi_arlen(shadow_core_outputs.ifu_axi_arlen),
1207 : .ifu_axi_arsize(shadow_core_outputs.ifu_axi_arsize),
1208 : .ifu_axi_arburst(shadow_core_outputs.ifu_axi_arburst),
1209 : .ifu_axi_arlock(shadow_core_outputs.ifu_axi_arlock),
1210 : .ifu_axi_arcache(shadow_core_outputs.ifu_axi_arcache),
1211 : .ifu_axi_arprot(shadow_core_outputs.ifu_axi_arprot),
1212 : .ifu_axi_arqos(shadow_core_outputs.ifu_axi_arqos),
1213 : .ifu_axi_rvalid(shadow_core_inputs.ifu_axi_rvalid),
1214 : .ifu_axi_rready(shadow_core_outputs.ifu_axi_rready),
1215 : .ifu_axi_rid(shadow_core_inputs.ifu_axi_rid),
1216 : .ifu_axi_rdata(shadow_core_inputs.ifu_axi_rdata),
1217 : .ifu_axi_rresp(shadow_core_inputs.ifu_axi_rresp),
1218 : .ifu_axi_rlast(shadow_core_inputs.ifu_axi_rlast),
1219 :
1220 : .sb_axi_awvalid(shadow_core_outputs.sb_axi_awvalid),
1221 : .sb_axi_awready(shadow_core_inputs.sb_axi_awready),
1222 : .sb_axi_awid(shadow_core_outputs.sb_axi_awid),
1223 : .sb_axi_awaddr(shadow_core_outputs.sb_axi_awaddr),
1224 : .sb_axi_awregion(shadow_core_outputs.sb_axi_awregion),
1225 : .sb_axi_awlen(shadow_core_outputs.sb_axi_awlen),
1226 : .sb_axi_awsize(shadow_core_outputs.sb_axi_awsize),
1227 : .sb_axi_awburst(shadow_core_outputs.sb_axi_awburst),
1228 : .sb_axi_awlock(shadow_core_outputs.sb_axi_awlock),
1229 : .sb_axi_awcache(shadow_core_outputs.sb_axi_awcache),
1230 : .sb_axi_awprot(shadow_core_outputs.sb_axi_awprot),
1231 : .sb_axi_awqos(shadow_core_outputs.sb_axi_awqos),
1232 : .sb_axi_wvalid(shadow_core_outputs.sb_axi_wvalid),
1233 : .sb_axi_wready(shadow_core_inputs.sb_axi_wready),
1234 : .sb_axi_wdata(shadow_core_outputs.sb_axi_wdata),
1235 : .sb_axi_wstrb(shadow_core_outputs.sb_axi_wstrb),
1236 : .sb_axi_wlast(shadow_core_outputs.sb_axi_wlast),
1237 : .sb_axi_bvalid(shadow_core_inputs.sb_axi_bvalid),
1238 : .sb_axi_bready(shadow_core_outputs.sb_axi_bready),
1239 : .sb_axi_bresp(shadow_core_inputs.sb_axi_bresp),
1240 : .sb_axi_bid(shadow_core_inputs.sb_axi_bid),
1241 : .sb_axi_arvalid(shadow_core_outputs.sb_axi_arvalid),
1242 : .sb_axi_arready(shadow_core_inputs.sb_axi_arready),
1243 : .sb_axi_arid(shadow_core_outputs.sb_axi_arid),
1244 : .sb_axi_araddr(shadow_core_outputs.sb_axi_araddr),
1245 : .sb_axi_arregion(shadow_core_outputs.sb_axi_arregion),
1246 : .sb_axi_arlen(shadow_core_outputs.sb_axi_arlen),
1247 : .sb_axi_arsize(shadow_core_outputs.sb_axi_arsize),
1248 : .sb_axi_arburst(shadow_core_outputs.sb_axi_arburst),
1249 : .sb_axi_arlock(shadow_core_outputs.sb_axi_arlock),
1250 : .sb_axi_arcache(shadow_core_outputs.sb_axi_arcache),
1251 : .sb_axi_arprot(shadow_core_outputs.sb_axi_arprot),
1252 : .sb_axi_arqos(shadow_core_outputs.sb_axi_arqos),
1253 : .sb_axi_rvalid(shadow_core_inputs.sb_axi_rvalid),
1254 : .sb_axi_rready(shadow_core_outputs.sb_axi_rready),
1255 : .sb_axi_rid(shadow_core_inputs.sb_axi_rid),
1256 : .sb_axi_rdata(shadow_core_inputs.sb_axi_rdata),
1257 : .sb_axi_rresp(shadow_core_inputs.sb_axi_rresp),
1258 : .sb_axi_rlast(shadow_core_inputs.sb_axi_rlast),
1259 :
1260 : .dma_axi_awvalid(shadow_core_inputs.dma_axi_awvalid),
1261 : .dma_axi_awready(shadow_core_outputs.dma_axi_awready),
1262 : .dma_axi_awid(shadow_core_inputs.dma_axi_awid),
1263 : .dma_axi_awaddr(shadow_core_inputs.dma_axi_awaddr),
1264 : .dma_axi_awsize(shadow_core_inputs.dma_axi_awsize),
1265 : .dma_axi_awprot(shadow_core_inputs.dma_axi_awprot),
1266 : .dma_axi_awlen(shadow_core_inputs.dma_axi_awlen),
1267 : .dma_axi_awburst(shadow_core_inputs.dma_axi_awburst),
1268 : .dma_axi_wvalid(shadow_core_inputs.dma_axi_wvalid),
1269 : .dma_axi_wready(shadow_core_outputs.dma_axi_wready),
1270 : .dma_axi_wdata(shadow_core_inputs.dma_axi_wdata),
1271 : .dma_axi_wstrb(shadow_core_inputs.dma_axi_wstrb),
1272 : .dma_axi_wlast(shadow_core_inputs.dma_axi_wlast),
1273 : .dma_axi_bvalid(shadow_core_outputs.dma_axi_bvalid),
1274 : .dma_axi_bready(shadow_core_inputs.dma_axi_bready),
1275 : .dma_axi_bresp(shadow_core_outputs.dma_axi_bresp),
1276 : .dma_axi_bid(shadow_core_outputs.dma_axi_bid),
1277 : .dma_axi_arvalid(shadow_core_inputs.dma_axi_arvalid),
1278 : .dma_axi_arready(shadow_core_outputs.dma_axi_arready),
1279 : .dma_axi_arid(shadow_core_inputs.dma_axi_arid),
1280 : .dma_axi_araddr(shadow_core_inputs.dma_axi_araddr),
1281 : .dma_axi_arsize(shadow_core_inputs.dma_axi_arsize),
1282 : .dma_axi_arprot(shadow_core_inputs.dma_axi_arprot),
1283 : .dma_axi_arlen(shadow_core_inputs.dma_axi_arlen),
1284 : .dma_axi_arburst(shadow_core_inputs.dma_axi_arburst),
1285 : .dma_axi_rvalid(shadow_core_outputs.dma_axi_rvalid),
1286 : .dma_axi_rready(shadow_core_inputs.dma_axi_rready),
1287 : .dma_axi_rid(shadow_core_outputs.dma_axi_rid),
1288 : .dma_axi_rdata(shadow_core_outputs.dma_axi_rdata),
1289 : .dma_axi_rresp(shadow_core_outputs.dma_axi_rresp),
1290 : .dma_axi_rlast(shadow_core_outputs.dma_axi_rlast),
1291 :
1292 : .haddr(shadow_core_outputs.haddr),
1293 : .hburst(shadow_core_outputs.hburst),
1294 : .hmastlock(shadow_core_outputs.hmastlock),
1295 : .hprot(shadow_core_outputs.hprot),
1296 : .hsize(shadow_core_outputs.hsize),
1297 : .htrans(shadow_core_outputs.htrans),
1298 : .hwrite(shadow_core_outputs.hwrite),
1299 : .hrdata(shadow_core_inputs.hrdata),
1300 : .hready(shadow_core_inputs.hready),
1301 : .hresp(shadow_core_inputs.hresp),
1302 :
1303 : .lsu_haddr(shadow_core_outputs.lsu_haddr),
1304 : .lsu_hburst(shadow_core_outputs.lsu_hburst),
1305 : .lsu_hmastlock(shadow_core_outputs.lsu_hmastlock),
1306 : .lsu_hprot(shadow_core_outputs.lsu_hprot),
1307 : .lsu_hsize(shadow_core_outputs.lsu_hsize),
1308 : .lsu_htrans(shadow_core_outputs.lsu_htrans),
1309 : .lsu_hwrite(shadow_core_outputs.lsu_hwrite),
1310 : .lsu_hwdata(shadow_core_outputs.lsu_hwdata),
1311 : .lsu_hrdata(shadow_core_inputs.lsu_hrdata),
1312 : .lsu_hready(shadow_core_inputs.lsu_hready),
1313 : .lsu_hresp(shadow_core_inputs.lsu_hresp),
1314 :
1315 : .sb_haddr(shadow_core_outputs.sb_haddr),
1316 : .sb_hburst(shadow_core_outputs.sb_hburst),
1317 : .sb_hmastlock(shadow_core_outputs.sb_hmastlock),
1318 : .sb_hprot(shadow_core_outputs.sb_hprot),
1319 : .sb_hsize(shadow_core_outputs.sb_hsize),
1320 : .sb_htrans(shadow_core_outputs.sb_htrans),
1321 : .sb_hwrite(shadow_core_outputs.sb_hwrite),
1322 : .sb_hwdata(shadow_core_outputs.sb_hwdata),
1323 : .sb_hrdata(shadow_core_inputs.sb_hrdata),
1324 : .sb_hready(shadow_core_inputs.sb_hready),
1325 : .sb_hresp(shadow_core_inputs.sb_hresp),
1326 :
1327 : .dma_hsel(shadow_core_inputs.dma_hsel),
1328 : .dma_haddr(shadow_core_inputs.dma_haddr),
1329 : .dma_hburst(shadow_core_inputs.dma_hburst),
1330 : .dma_hmastlock(shadow_core_inputs.dma_hmastlock),
1331 : .dma_hprot(shadow_core_inputs.dma_hprot),
1332 : .dma_hsize(shadow_core_inputs.dma_hsize),
1333 : .dma_htrans(shadow_core_inputs.dma_htrans),
1334 : .dma_hwrite(shadow_core_inputs.dma_hwrite),
1335 : .dma_hwdata(shadow_core_inputs.dma_hwdata),
1336 : .dma_hreadyin(shadow_core_inputs.dma_hreadyin),
1337 : .dma_hrdata(shadow_core_outputs.dma_hrdata),
1338 : .dma_hreadyout(shadow_core_outputs.dma_hreadyout),
1339 : .dma_hresp(shadow_core_outputs.dma_hresp),
1340 :
1341 : .lsu_bus_clk_en(shadow_core_inputs.lsu_bus_clk_en),
1342 : .ifu_bus_clk_en(shadow_core_inputs.ifu_bus_clk_en),
1343 : .dbg_bus_clk_en(shadow_core_inputs.dbg_bus_clk_en),
1344 : .dma_bus_clk_en(shadow_core_inputs.dma_bus_clk_en),
1345 :
1346 : .dmi_reg_en(shadow_core_inputs.dmi_reg_en),
1347 : .dmi_reg_addr(shadow_core_inputs.dmi_reg_addr),
1348 : .dmi_reg_wr_en(shadow_core_inputs.dmi_reg_wr_en),
1349 : .dmi_reg_wdata(shadow_core_inputs.dmi_reg_wdata),
1350 : .dmi_reg_rdata(shadow_core_outputs.dmi_reg_rdata),
1351 :
1352 : .iccm_ecc_single_error(shadow_core_outputs.iccm_ecc_single_error),
1353 : .iccm_ecc_double_error(shadow_core_outputs.iccm_ecc_double_error),
1354 : .dccm_ecc_single_error(shadow_core_outputs.dccm_ecc_single_error),
1355 : .dccm_ecc_double_error(shadow_core_outputs.dccm_ecc_double_error),
1356 :
1357 : .extintsrc_req(shadow_core_inputs.extintsrc_req),
1358 : .timer_int(shadow_core_inputs.timer_int),
1359 : .soft_int(shadow_core_inputs.soft_int),
1360 : .scan_mode(shadow_core_inputs.scan_mode)
1361 : );
1362 :
1363 : // Equivalence Check
1364 3 : logic rst_n;
1365 : assign rst_n = rst_shadow & rst_dbg_shadow;
1366 :
1367 4 : logic corruption_detected, outputs_corrupted;
1368 : assign outputs_corrupted = delayed_main_core_outputs != shadow_core_outputs;
1369 :
1370 : `ifdef RV_LOCKSTEP_REGFILE_ENABLE
1371 4 : logic regfile_corrupted;
1372 : assign regfile_corrupted = (delayed_main_core_regfile[LockstepDelay].gpr != shadow_core_regfile.gpr)
1373 : | (delayed_main_core_regfile[LockstepDelay].tlu != shadow_core_regfile.tlu);
1374 : assign corruption_detected = outputs_corrupted | regfile_corrupted;
1375 : `else
1376 : assign corruption_detected = outputs_corrupted;
1377 : `endif
1378 :
1379 : // Report corruption if all of the below requirements are fulfilled:
1380 : // - IOs of Main Core and Shadow Core differ OR error injection is enabled
1381 : // - Shadow Core is out of reset
1382 : // - Shadow Core is enabled
1383 : assign corruption_detected_o = ((corruption_detected | lockstep_err_injection_en_i) & rst_n) & ~disable_corruption_detection_i;
1384 :
1385 : endmodule : el2_veer_lockstep
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