Project Full coverage report
Current view: Cores-VeeR-EL2—Cores-VeeR-EL2—design—el2_veer.sv Coverage Hit Total
Test Date: 19-11-2024 Toggle 74.7% 420 562
Test: all Branch 0.0% 0 0

            Line data    Source code
       1              : // SPDX-License-Identifier: Apache-2.0
       2              : // Copyright 2020 Western Digital Corporation or its affiliates.
       3              : //
       4              : // Licensed under the Apache License, Version 2.0 (the "License");
       5              : // you may not use this file except in compliance with the License.
       6              : // You may obtain a copy of the License at
       7              : //
       8              : // http://www.apache.org/licenses/LICENSE-2.0
       9              : //
      10              : // Unless required by applicable law or agreed to in writing, software
      11              : // distributed under the License is distributed on an "AS IS" BASIS,
      12              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      13              : // See the License for the specific language governing permissions and
      14              : // limitations under the License.
      15              : 
      16              : //********************************************************************************
      17              : // $Id$
      18              : //
      19              : // Function: Top level VeeR core file
      20              : // Comments:
      21              : //
      22              : //********************************************************************************
      23              : module el2_veer
      24              : import el2_pkg::*;
      25              : #(
      26              : `include "el2_param.vh"
      27              :  )
      28              :   (
      29     69881769 :    input logic                  clk,
      30          344 :    input logic                  rst_l,
      31          344 :    input logic                  dbg_rst_l,
      32            0 :    input logic [31:1]           rst_vec,
      33            2 :    input logic                  nmi_int,
      34           16 :    input logic [31:1]           nmi_vec,
      35          344 :    output logic                 core_rst_l,   // This is "rst_l | dbg_rst_l"
      36              : 
      37     69881769 :    output logic                 active_l2clk,
      38     69881769 :    output logic                 free_l2clk,
      39              : 
      40       579463 :    output logic [31:0] trace_rv_i_insn_ip,
      41          339 :    output logic [31:0] trace_rv_i_address_ip,
      42      6172835 :    output logic   trace_rv_i_valid_ip,
      43         5204 :    output logic   trace_rv_i_exception_ip,
      44            4 :    output logic [4:0]  trace_rv_i_ecause_ip,
      45           24 :    output logic   trace_rv_i_interrupt_ip,
      46           62 :    output logic [31:0] trace_rv_i_tval_ip,
      47              : 
      48              : 
      49            2 :    output logic                 dccm_clk_override,
      50            2 :    output logic                 icm_clk_override,
      51            8 :    output logic                 dec_tlu_core_ecc_disable,
      52              : 
      53              :    // external halt/run interface
      54          108 :    input logic  i_cpu_halt_req,    // Asynchronous Halt request to CPU
      55          108 :    input logic  i_cpu_run_req,     // Asynchronous Restart request to CPU
      56          108 :    output logic o_cpu_halt_ack,    // Core Acknowledge to Halt request
      57          108 :    output logic o_cpu_halt_status, // 1'b1 indicates processor is halted
      58          108 :    output logic o_cpu_run_ack,     // Core Acknowledge to run request
      59          124 :    output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
      60              : 
      61            0 :    input logic [31:4] core_id, // CORE ID
      62              : 
      63              :    // external MPC halt/run interface
      64          108 :    input logic mpc_debug_halt_req, // Async halt request
      65          108 :    input logic mpc_debug_run_req, // Async run request
      66          338 :    input logic mpc_reset_run_req, // Run/halt after reset
      67          108 :    output logic mpc_debug_halt_ack, // Halt ack
      68          108 :    output logic mpc_debug_run_ack, // Run ack
      69            2 :    output logic debug_brkpt_status, // debug breakpoint
      70              : 
      71       340148 :    output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
      72       514626 :    output logic dec_tlu_perfcnt1,
      73       312914 :    output logic dec_tlu_perfcnt2,
      74        48468 :    output logic dec_tlu_perfcnt3,
      75              : 
      76              :    // DCCM ports
      77       262894 :    output logic                          dccm_wren,
      78       561000 :    output logic                          dccm_rden,
      79        18811 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_lo,
      80        18811 :    output logic [pt.DCCM_BITS-1:0]          dccm_wr_addr_hi,
      81       471334 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_lo,
      82       677729 :    output logic [pt.DCCM_BITS-1:0]          dccm_rd_addr_hi,
      83         5376 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_lo,
      84         5376 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]   dccm_wr_data_hi,
      85              : 
      86        47176 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]    dccm_rd_data_lo,
      87        47176 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]    dccm_rd_data_hi,
      88              : 
      89              :    // ICCM ports
      90       160274 :    output logic [pt.ICCM_BITS-1:1]           iccm_rw_addr,
      91           74 :    output logic                  iccm_wren,
      92       133206 :    output logic                  iccm_rden,
      93            0 :    output logic [2:0]            iccm_wr_size,
      94           14 :    output logic [77:0]           iccm_wr_data,
      95            8 :    output logic                  iccm_buf_correct_ecc,
      96            8 :    output logic                  iccm_correction_state,
      97              : 
      98       136532 :    input  logic [63:0]          iccm_rd_data,
      99       161264 :    input  logic [77:0]           iccm_rd_data_ecc,
     100              : 
     101              :    // ICache , ITAG  ports
     102          489 :    output logic [31:1]           ic_rw_addr,
     103       255918 :    output logic [pt.ICACHE_NUM_WAYS-1:0]            ic_tag_valid,
     104        10432 :    output logic [pt.ICACHE_NUM_WAYS-1:0]            ic_wr_en,
     105       680938 :    output logic                  ic_rd_en,
     106              : 
     107       560643 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
     108      2137084 :    input  logic [63:0]               ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
     109       231581 :    input  logic [70:0]               ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
     110            0 :    input  logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
     111            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
     112              : 
     113            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
     114            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
     115      1738674 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
     116      5605560 :    output logic                      ic_sel_premux_data, // Select premux data
     117              : 
     118              : 
     119            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
     120           20 :    output logic                      ic_debug_rd_en,     // Icache debug rd
     121           20 :    output logic                      ic_debug_wr_en,     // Icache debug wr
     122            8 :    output logic                      ic_debug_tag_array, // Debug tag array
     123            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
     124              : 
     125              : 
     126              : 
     127       109586 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]            ic_rd_hit,
     128            0 :    input  logic                  ic_tag_perr,        // Icache Tag parity error
     129              : 
     130              :    //-------------------------- LSU AXI signals--------------------------
     131              :    // AXI Write Channels
     132       863100 :    output logic                            lsu_axi_awvalid,
     133       669068 :    input  logic                            lsu_axi_awready,
     134            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
     135          292 :    output logic [31:0]                     lsu_axi_awaddr,
     136          336 :    output logic [3:0]                      lsu_axi_awregion,
     137              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     138              :    /*verilator coverage_off*/
     139              :    output logic [7:0]                      lsu_axi_awlen,
     140              :    /*verilator coverage_on*/
     141            0 :    output logic [2:0]                      lsu_axi_awsize,
     142              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     143              :    /*verilator coverage_off*/
     144              :    output logic [1:0]                      lsu_axi_awburst,
     145              :    output logic                            lsu_axi_awlock,
     146              :    /*verilator coverage_on*/
     147         3031 :    output logic [3:0]                      lsu_axi_awcache,
     148              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     149              :    /*verilator coverage_off*/
     150              :    output logic [2:0]                      lsu_axi_awprot,
     151              :    output logic [3:0]                      lsu_axi_awqos,
     152              :    /*verilator coverage_on*/
     153              : 
     154       863100 :    output logic                            lsu_axi_wvalid,
     155       669068 :    input  logic                            lsu_axi_wready,
     156        31437 :    output logic [63:0]                     lsu_axi_wdata,
     157       225031 :    output logic [7:0]                      lsu_axi_wstrb,
     158          341 :    output logic                            lsu_axi_wlast,
     159              : 
     160       668810 :    input  logic                            lsu_axi_bvalid,
     161              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     162              :    /*verilator coverage_off*/
     163              :    output logic                            lsu_axi_bready,
     164              :    /*verilator coverage_on*/
     165            2 :    input  logic [1:0]                      lsu_axi_bresp,
     166            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
     167              : 
     168              :    // AXI Read Channels
     169       868996 :    output logic                            lsu_axi_arvalid,
     170       673312 :    input  logic                            lsu_axi_arready,
     171            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
     172          292 :    output logic [31:0]                     lsu_axi_araddr,
     173          336 :    output logic [3:0]                      lsu_axi_arregion,
     174              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     175              :    /*verilator coverage_off*/
     176              :    output logic [7:0]                      lsu_axi_arlen,
     177              :    /*verilator coverage_on*/
     178            0 :    output logic [2:0]                      lsu_axi_arsize,
     179              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     180              :    /*verilator coverage_off*/
     181              :    output logic [1:0]                      lsu_axi_arburst,
     182              :    output logic                            lsu_axi_arlock,
     183              :    /*verilator coverage_on*/
     184         3031 :    output logic [3:0]                      lsu_axi_arcache,
     185              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     186              :    /*verilator coverage_off*/
     187              :    output logic [2:0]                      lsu_axi_arprot,
     188              :    output logic [3:0]                      lsu_axi_arqos,
     189              :    /*verilator coverage_on*/
     190              : 
     191       672996 :    input  logic                            lsu_axi_rvalid,
     192              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     193              :    /*verilator coverage_off*/
     194              :    output logic                            lsu_axi_rready,
     195              :    /*verilator coverage_on*/
     196            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
     197        26505 :    input  logic [63:0]                     lsu_axi_rdata,
     198            2 :    input  logic [1:0]                      lsu_axi_rresp,
     199       673648 :    input  logic                            lsu_axi_rlast,
     200              : 
     201              :    //-------------------------- IFU AXI signals--------------------------
     202              :    // AXI Write Channels
     203              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     204              :    /*verilator coverage_off*/
     205              :    output logic                            ifu_axi_awvalid,
     206              :    /*verilator coverage_on*/
     207           20 :    input  logic                            ifu_axi_awready,
     208              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     209              :    /*verilator coverage_off*/
     210              :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_awid,
     211              :    output logic [31:0]                     ifu_axi_awaddr,
     212              :    output logic [3:0]                      ifu_axi_awregion,
     213              :    output logic [7:0]                      ifu_axi_awlen,
     214              :    output logic [2:0]                      ifu_axi_awsize,
     215              :    output logic [1:0]                      ifu_axi_awburst,
     216              :    output logic                            ifu_axi_awlock,
     217              :    output logic [3:0]                      ifu_axi_awcache,
     218              :    output logic [2:0]                      ifu_axi_awprot,
     219              :    output logic [3:0]                      ifu_axi_awqos,
     220              : 
     221              :    output logic                            ifu_axi_wvalid,
     222              :    /*verilator coverage_on*/
     223           20 :    input  logic                            ifu_axi_wready,
     224              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     225              :    /*verilator coverage_off*/
     226              :    output logic [63:0]                     ifu_axi_wdata,
     227              :    output logic [7:0]                      ifu_axi_wstrb,
     228              :    output logic                            ifu_axi_wlast,
     229              :    /*verilator coverage_on*/
     230              : 
     231            0 :    input  logic                            ifu_axi_bvalid,
     232              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     233              :    /*verilator coverage_off*/
     234              :    output logic                            ifu_axi_bready,
     235              :    /*verilator coverage_on*/
     236            0 :    input  logic [1:0]                      ifu_axi_bresp,
     237            0 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_bid,
     238              : 
     239              :    // AXI Read Channels
     240      5895060 :    output logic                            ifu_axi_arvalid,
     241      8918851 :    input  logic                            ifu_axi_arready,
     242      3590104 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
     243      2455058 :    output logic [31:0]                     ifu_axi_araddr,
     244          545 :    output logic [3:0]                      ifu_axi_arregion,
     245              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     246              :    /*verilator coverage_off*/
     247              :    output logic [7:0]                      ifu_axi_arlen,
     248              :    output logic [2:0]                      ifu_axi_arsize,
     249              :    output logic [1:0]                      ifu_axi_arburst,
     250              :    output logic                            ifu_axi_arlock,
     251              :    output logic [3:0]                      ifu_axi_arcache,
     252              :    output logic [2:0]                      ifu_axi_arprot,
     253              :    output logic [3:0]                      ifu_axi_arqos,
     254              :    /*verilator coverage_on*/
     255              : 
     256      8918533 :    input  logic                            ifu_axi_rvalid,
     257              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     258              :    /*verilator coverage_off*/
     259              :    output logic                            ifu_axi_rready,
     260              :    /*verilator coverage_on*/
     261       897578 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
     262       744653 :    input  logic [63:0]                     ifu_axi_rdata,
     263           20 :    input  logic [1:0]                      ifu_axi_rresp,
     264      8918533 :    input  logic                            ifu_axi_rlast,
     265              : 
     266              :    //-------------------------- SB AXI signals--------------------------
     267              :    // AXI Write Channels
     268          244 :    output logic                            sb_axi_awvalid,
     269          122 :    input  logic                            sb_axi_awready,
     270              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     271              :    /*verilator coverage_off*/
     272              :    output logic [pt.SB_BUS_TAG-1:0]        sb_axi_awid,
     273              :    /*verilator coverage_on*/
     274            4 :    output logic [31:0]                     sb_axi_awaddr,
     275          196 :    output logic [3:0]                      sb_axi_awregion,
     276              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     277              :    /*verilator coverage_off*/
     278              :    output logic [7:0]                      sb_axi_awlen,
     279              :    /*verilator coverage_on*/
     280            0 :    output logic [2:0]                      sb_axi_awsize,
     281              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     282              :    /*verilator coverage_off*/
     283              :    output logic [1:0]                      sb_axi_awburst,
     284              :    output logic                            sb_axi_awlock,
     285              :    output logic [3:0]                      sb_axi_awcache,
     286              :    output logic [2:0]                      sb_axi_awprot,
     287              :    output logic [3:0]                      sb_axi_awqos,
     288              :    /*verilator coverage_on*/
     289              : 
     290          244 :    output logic                            sb_axi_wvalid,
     291          122 :    input  logic                            sb_axi_wready,
     292           62 :    output logic [63:0]                     sb_axi_wdata,
     293          536 :    output logic [7:0]                      sb_axi_wstrb,
     294          341 :    output logic                            sb_axi_wlast,
     295              : 
     296          122 :    input  logic                            sb_axi_bvalid,
     297          341 :    output logic                            sb_axi_bready,
     298            0 :    input  logic [1:0]                      sb_axi_bresp,
     299            0 :    input  logic [pt.SB_BUS_TAG-1:0]        sb_axi_bid,
     300              : 
     301              :    // AXI Read Channels
     302         1504 :    output logic                            sb_axi_arvalid,
     303          652 :    input  logic                            sb_axi_arready,
     304              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     305              :    /*verilator coverage_off*/
     306              :    output logic [pt.SB_BUS_TAG-1:0]        sb_axi_arid,
     307              :    /*verilator coverage_on*/
     308            4 :    output logic [31:0]                     sb_axi_araddr,
     309          196 :    output logic [3:0]                      sb_axi_arregion,
     310              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     311              :    /*verilator coverage_off*/
     312              :    output logic [7:0]                      sb_axi_arlen,
     313              :    /*verilator coverage_on*/
     314            0 :    output logic [2:0]                      sb_axi_arsize,
     315              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     316              :    /*verilator coverage_off*/
     317              :    output logic [1:0]                      sb_axi_arburst,
     318              :    output logic                            sb_axi_arlock,
     319              :    output logic [3:0]                      sb_axi_arcache,
     320              :    output logic [2:0]                      sb_axi_arprot,
     321              :    output logic [3:0]                      sb_axi_arqos,
     322              :    /*verilator coverage_on*/
     323              : 
     324          652 :    input  logic                            sb_axi_rvalid,
     325              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     326              :    /*verilator coverage_off*/
     327              :    output logic                            sb_axi_rready,
     328              :    /*verilator coverage_on*/
     329            0 :    input  logic [pt.SB_BUS_TAG-1:0]        sb_axi_rid,
     330            5 :    input  logic [63:0]                     sb_axi_rdata,
     331            0 :    input  logic [1:0]                      sb_axi_rresp,
     332          652 :    input  logic                            sb_axi_rlast,
     333              : 
     334              :    //-------------------------- DMA AXI signals--------------------------
     335              :    // AXI Write Channels
     336           66 :    input  logic                         dma_axi_awvalid,
     337          341 :    output logic                         dma_axi_awready,
     338            0 :    input  logic [pt.DMA_BUS_TAG-1:0]    dma_axi_awid,
     339          282 :    input  logic [31:0]                  dma_axi_awaddr,
     340            0 :    input  logic [2:0]                   dma_axi_awsize,
     341            0 :    input  logic [2:0]                   dma_axi_awprot,
     342            0 :    input  logic [7:0]                   dma_axi_awlen,
     343            0 :    input  logic [1:0]                   dma_axi_awburst,
     344              : 
     345              : 
     346           66 :    input  logic                         dma_axi_wvalid,
     347          341 :    output logic                         dma_axi_wready,
     348        29795 :    input  logic [63:0]                  dma_axi_wdata,
     349       185761 :    input  logic [7:0]                   dma_axi_wstrb,
     350          318 :    input  logic                         dma_axi_wlast,
     351              : 
     352           66 :    output logic                         dma_axi_bvalid,
     353           66 :    input  logic                         dma_axi_bready,
     354            4 :    output logic [1:0]                   dma_axi_bresp,
     355            0 :    output logic [pt.DMA_BUS_TAG-1:0]    dma_axi_bid,
     356              : 
     357              :    // AXI Read Channels
     358            0 :    input  logic                         dma_axi_arvalid,
     359          341 :    output logic                         dma_axi_arready,
     360            0 :    input  logic [pt.DMA_BUS_TAG-1:0]    dma_axi_arid,
     361          282 :    input  logic [31:0]                  dma_axi_araddr,
     362            0 :    input  logic [2:0]                   dma_axi_arsize,
     363            0 :    input  logic [2:0]                   dma_axi_arprot,
     364            0 :    input  logic [7:0]                   dma_axi_arlen,
     365            0 :    input  logic [1:0]                   dma_axi_arburst,
     366              : 
     367            0 :    output logic                         dma_axi_rvalid,
     368            0 :    input  logic                         dma_axi_rready,
     369            0 :    output logic [pt.DMA_BUS_TAG-1:0]    dma_axi_rid,
     370           12 :    output logic [63:0]                  dma_axi_rdata,
     371            4 :    output logic [1:0]                   dma_axi_rresp,
     372          341 :    output logic                         dma_axi_rlast,
     373              : 
     374              : 
     375              :  //// AHB LITE BUS
     376           17 :    output logic [31:0]           haddr,
     377              :    /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
     378              :    /*verilator coverage_off*/
     379              :    output logic [2:0]            hburst,
     380              :    output logic                  hmastlock,
     381              :    /*verilator coverage_on*/
     382            0 :    output logic [3:0]            hprot,
     383            0 :    output logic [2:0]            hsize,
     384      1445565 :    output logic [1:0]            htrans,
     385            0 :    output logic                  hwrite,
     386              : 
     387       240901 :    input  logic [63:0]           hrdata,
     388           20 :    input  logic                  hready,
     389            0 :    input  logic                  hresp,
     390              : 
     391              :    // LSU AHB Master
     392           10 :    output logic [31:0]          lsu_haddr,
     393              :    /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
     394              :    /*verilator coverage_off*/
     395              :    output logic [2:0]           lsu_hburst,
     396              :    output logic                 lsu_hmastlock,
     397              :    /*verilator coverage_on*/
     398            0 :    output logic [3:0]           lsu_hprot,
     399            0 :    output logic [2:0]           lsu_hsize,
     400       445316 :    output logic [1:0]           lsu_htrans,
     401        89186 :    output logic                 lsu_hwrite,
     402         5340 :    output logic [63:0]          lsu_hwdata,
     403              : 
     404         2335 :    input  logic [63:0]          lsu_hrdata,
     405           20 :    input  logic                 lsu_hready,
     406            0 :    input  logic                 lsu_hresp,
     407              : 
     408              :    //System Bus Debug Master
     409            2 :    output logic [31:0]          sb_haddr,
     410              :    /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
     411              :    /*verilator coverage_off*/
     412              :    output logic [2:0]           sb_hburst,
     413              :    output logic                 sb_hmastlock,
     414              :    /*verilator coverage_on*/
     415            0 :    output logic [3:0]           sb_hprot,
     416            0 :    output logic [2:0]           sb_hsize,
     417          974 :    output logic [1:0]           sb_htrans,
     418          119 :    output logic                 sb_hwrite,
     419           35 :    output logic [63:0]          sb_hwdata,
     420              : 
     421            8 :    input  logic [63:0]          sb_hrdata,
     422            2 :    input  logic                 sb_hready,
     423            0 :    input  logic                 sb_hresp,
     424              : 
     425              :    // DMA Slave
     426           20 :    input logic                   dma_hsel,
     427            0 :    input logic [31:0]            dma_haddr,
     428            0 :    input logic [2:0]             dma_hburst,
     429            0 :    input logic                   dma_hmastlock,
     430            0 :    input logic [3:0]             dma_hprot,
     431            0 :    input logic [2:0]             dma_hsize,
     432            0 :    input logic [1:0]             dma_htrans,
     433            0 :    input logic                   dma_hwrite,
     434            0 :    input logic [63:0]            dma_hwdata,
     435           20 :    input logic                   dma_hreadyin,
     436              : 
     437            0 :    output  logic [63:0]          dma_hrdata,
     438           20 :    output  logic                 dma_hreadyout,
     439            0 :    output  logic                 dma_hresp,
     440              : 
     441          338 :    input   logic                 lsu_bus_clk_en,
     442          338 :    input   logic                 ifu_bus_clk_en,
     443          338 :    input   logic                 dbg_bus_clk_en,
     444          338 :    input   logic                 dma_bus_clk_en,
     445              : 
     446        16990 :    input logic                  dmi_reg_en,                // read or write
     447            0 :    input logic [6:0]            dmi_reg_addr,              // address of DM register
     448         6308 :    input logic                  dmi_reg_wr_en,             // write instruction
     449           86 :    input logic [31:0]           dmi_reg_wdata,             // write data
     450          112 :    output logic [31:0]          dmi_reg_rdata,
     451              : 
     452              :    // ICCM/DCCM ECC status
     453            8 :    output logic                 iccm_ecc_single_error,
     454            4 :    output logic                 iccm_ecc_double_error,
     455            4 :    output logic                 dccm_ecc_single_error,
     456            4 :    output logic                 dccm_ecc_double_error,
     457              : 
     458              : `ifdef RV_LOCKSTEP_REGFILE_ENABLE
     459              :    // Register file
     460              :    el2_regfile_if.veer_rf_src regfile,
     461              : `endif
     462              : 
     463            0 :    input logic [pt.PIC_TOTAL_INT:1]           extintsrc_req,
     464           16 :    input logic                   timer_int,
     465           15 :    input logic                   soft_int,
     466              :    // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
     467              :    /*verilator coverage_off*/
     468              :    input logic                   scan_mode
     469              :    /*verilator coverage_on*/
     470              : );
     471              : 
     472              : 
     473              : 
     474              : 
     475       192575 :    logic [63:0]                  hwdata_nc;
     476              :    //----------------------------------------------------------------------
     477              :    //
     478              :    //----------------------------------------------------------------------
     479              : 
     480      6202516 :    logic                         ifu_pmu_instr_aligned;
     481            0 :    logic                         ifu_ic_error_start;
     482            0 :    logic                         ifu_iccm_dma_rd_ecc_single_err;
     483            8 :    logic                         ifu_iccm_rd_ecc_single_err;
     484            4 :    logic                         ifu_iccm_rd_ecc_double_err;
     485            4 :    logic                         lsu_dccm_rd_ecc_single_err;
     486            4 :    logic                         lsu_dccm_rd_ecc_double_err;
     487              : 
     488       446199 :    logic                         lsu_axi_awready_ahb;
     489       446199 :    logic                         lsu_axi_wready_ahb;
     490       207518 :    logic                         lsu_axi_bvalid_ahb;
     491            0 :    logic                         lsu_axi_bready_ahb;
     492            0 :    logic [1:0]                   lsu_axi_bresp_ahb;
     493            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_ahb;
     494       442137 :    logic                         lsu_axi_arready_ahb;
     495       256790 :    logic                         lsu_axi_rvalid_ahb;
     496            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_ahb;
     497         2335 :    logic [63:0]                  lsu_axi_rdata_ahb;
     498            0 :    logic [1:0]                   lsu_axi_rresp_ahb;
     499           20 :    logic                         lsu_axi_rlast_ahb;
     500              : 
     501      1115267 :    logic                         lsu_axi_awready_int;
     502      1115267 :    logic                         lsu_axi_wready_int;
     503       876328 :    logic                         lsu_axi_bvalid_int;
     504          321 :    logic                         lsu_axi_bready_int;
     505            2 :    logic [1:0]                   lsu_axi_bresp_int;
     506            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_bid_int;
     507      1115449 :    logic                         lsu_axi_arready_int;
     508       929786 :    logic                         lsu_axi_rvalid_int;
     509            0 :    logic [pt.LSU_BUS_TAG-1:0]    lsu_axi_rid_int;
     510        28840 :    logic [63:0]                  lsu_axi_rdata_int;
     511            2 :    logic [1:0]                   lsu_axi_rresp_int;
     512       673668 :    logic                         lsu_axi_rlast_int;
     513              : 
     514      1445579 :    logic                         ifu_axi_awready_ahb;
     515      1445579 :    logic                         ifu_axi_wready_ahb;
     516            0 :    logic                         ifu_axi_bvalid_ahb;
     517            0 :    logic                         ifu_axi_bready_ahb;
     518            0 :    logic [1:0]                   ifu_axi_bresp_ahb;
     519       285070 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_ahb;
     520      1445579 :    logic                         ifu_axi_arready_ahb;
     521      2891121 :    logic                         ifu_axi_rvalid_ahb;
     522       285070 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_ahb;
     523       240900 :    logic [63:0]                  ifu_axi_rdata_ahb;
     524            0 :    logic [1:0]                   ifu_axi_rresp_ahb;
     525           20 :    logic                         ifu_axi_rlast_ahb;
     526              : 
     527      1445579 :    logic                         ifu_axi_awready_int;
     528      1445579 :    logic                         ifu_axi_wready_int;
     529            0 :    logic                         ifu_axi_bvalid_int;
     530            0 :    logic                         ifu_axi_bready_int;
     531            0 :    logic [1:0]                   ifu_axi_bresp_int;
     532       285070 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_bid_int;
     533     10364430 :    logic                         ifu_axi_arready_int;
     534     11809654 :    logic                         ifu_axi_rvalid_int;
     535      1182648 :    logic [pt.IFU_BUS_TAG-1:0]    ifu_axi_rid_int;
     536       985553 :    logic [63:0]                  ifu_axi_rdata_int;
     537           20 :    logic [1:0]                   ifu_axi_rresp_int;
     538      8918553 :    logic                         ifu_axi_rlast_int;
     539              : 
     540          994 :    logic                         sb_axi_awready_ahb;
     541          994 :    logic                         sb_axi_wready_ahb;
     542          122 :    logic                         sb_axi_bvalid_ahb;
     543            0 :    logic                         sb_axi_bready_ahb;
     544            0 :    logic [1:0]                   sb_axi_bresp_ahb;
     545            0 :    logic [pt.SB_BUS_TAG-1:0]     sb_axi_bid_ahb;
     546          994 :    logic                         sb_axi_arready_ahb;
     547          852 :    logic                         sb_axi_rvalid_ahb;
     548            0 :    logic [pt.SB_BUS_TAG-1:0]     sb_axi_rid_ahb;
     549            8 :    logic [63:0]                  sb_axi_rdata_ahb;
     550            0 :    logic [1:0]                   sb_axi_rresp_ahb;
     551           20 :    logic                         sb_axi_rlast_ahb;
     552              : 
     553         1116 :    logic                         sb_axi_awready_int;
     554         1116 :    logic                         sb_axi_wready_int;
     555          244 :    logic                         sb_axi_bvalid_int;
     556          321 :    logic                         sb_axi_bready_int;
     557            0 :    logic [1:0]                   sb_axi_bresp_int;
     558            0 :    logic [pt.SB_BUS_TAG-1:0]     sb_axi_bid_int;
     559         1646 :    logic                         sb_axi_arready_int;
     560         1504 :    logic                         sb_axi_rvalid_int;
     561            0 :    logic [pt.SB_BUS_TAG-1:0]     sb_axi_rid_int;
     562           13 :    logic [63:0]                  sb_axi_rdata_int;
     563            0 :    logic [1:0]                   sb_axi_rresp_int;
     564          672 :    logic                         sb_axi_rlast_int;
     565              : 
     566            0 :    logic                         dma_axi_awvalid_ahb;
     567              :    /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
     568              :    /*verilator coverage_off*/
     569              :    logic [pt.DMA_BUS_TAG-1:0]    dma_axi_awid_ahb;
     570              :    /*verilator coverage_on*/
     571            0 :    logic [31:0]                  dma_axi_awaddr_ahb;
     572            0 :    logic [2:0]                   dma_axi_awsize_ahb;
     573              :    /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
     574              :    /*verilator coverage_off*/
     575              :    logic [2:0]                   dma_axi_awprot_ahb;
     576              :    logic [7:0]                   dma_axi_awlen_ahb;
     577              :    logic [1:0]                   dma_axi_awburst_ahb;
     578              :    /*verilator coverage_on*/
     579            0 :    logic                         dma_axi_wvalid_ahb;
     580            0 :    logic [63:0]                  dma_axi_wdata_ahb;
     581            0 :    logic [7:0]                   dma_axi_wstrb_ahb;
     582              :    /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
     583              :    /*verilator coverage_off*/
     584              :    logic                         dma_axi_wlast_ahb;
     585              :    logic                         dma_axi_bready_ahb;
     586              :    /*verilator coverage_on*/
     587            0 :    logic                         dma_axi_arvalid_ahb;
     588              :    /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
     589              :    /*verilator coverage_off*/
     590              :    logic [pt.DMA_BUS_TAG-1:0]    dma_axi_arid_ahb;
     591              :    /*verilator coverage_on*/
     592            0 :    logic [31:0]                  dma_axi_araddr_ahb;
     593            0 :    logic [2:0]                   dma_axi_arsize_ahb;
     594              :    /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
     595              :    /*verilator coverage_off*/
     596              :    logic [2:0]                   dma_axi_arprot_ahb;
     597              :    logic [7:0]                   dma_axi_arlen_ahb;
     598              :    logic [1:0]                   dma_axi_arburst_ahb;
     599              :    logic                         dma_axi_rready_ahb;
     600              :    /*verilator coverage_on*/
     601              : 
     602           66 :    logic                         dma_axi_awvalid_int;
     603            0 :    logic [pt.DMA_BUS_TAG-1:0]    dma_axi_awid_int;
     604          282 :    logic [31:0]                  dma_axi_awaddr_int;
     605            0 :    logic [2:0]                   dma_axi_awsize_int;
     606            0 :    logic [2:0]                   dma_axi_awprot_int;
     607            0 :    logic [7:0]                   dma_axi_awlen_int;
     608            0 :    logic [1:0]                   dma_axi_awburst_int;
     609           66 :    logic                         dma_axi_wvalid_int;
     610        29795 :    logic [63:0]                  dma_axi_wdata_int;
     611       185761 :    logic [7:0]                   dma_axi_wstrb_int;
     612          338 :    logic                         dma_axi_wlast_int;
     613           86 :    logic                         dma_axi_bready_int;
     614            0 :    logic                         dma_axi_arvalid_int;
     615            0 :    logic [pt.DMA_BUS_TAG-1:0]    dma_axi_arid_int;
     616          282 :    logic [31:0]                  dma_axi_araddr_int;
     617            0 :    logic [2:0]                   dma_axi_arsize_int;
     618            0 :    logic [2:0]                   dma_axi_arprot_int;
     619            0 :    logic [7:0]                   dma_axi_arlen_int;
     620            0 :    logic [1:0]                   dma_axi_arburst_int;
     621           20 :    logic                         dma_axi_rready_int;
     622              : 
     623              : 
     624              : // Icache debug
     625            0 :    logic [70:0] ifu_ic_debug_rd_data; // diagnostic icache read data
     626           20 :    logic ifu_ic_debug_rd_data_valid; // diagnostic icache read data valid
     627            0 :    el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
     628              : 
     629              : 
     630      5140673 :    logic         dec_i0_rs1_en_d;
     631      3572727 :    logic         dec_i0_rs2_en_d;
     632       407930 :    logic  [31:0] gpr_i0_rs1_d;
     633       598748 :    logic  [31:0] gpr_i0_rs2_d;
     634              : 
     635       314097 :    logic [31:0] dec_i0_result_r;
     636       614725 :    logic [31:0] exu_i0_result_x;
     637          339 :    logic [31:1] exu_i0_pc_x;
     638          344 :    logic [31:1] exu_npc_r;
     639              : 
     640         1460 :    el2_alu_pkt_t  i0_ap;
     641              : 
     642              :    // Trigger signals
     643            0 :    el2_trigger_pkt_t [3:0]     trigger_pkt_any;
     644            0 :    logic [3:0]             lsu_trigger_match_m;
     645              : 
     646              : 
     647      2169832 :    logic [31:0] dec_i0_immed_d;
     648       123654 :    logic [12:1] dec_i0_br_immed_d;
     649       555743 :    logic         dec_i0_select_pc_d;
     650              : 
     651         1321 :    logic [31:1] dec_i0_pc_d;
     652        80590 :    logic [3:0]  dec_i0_rs1_bypass_en_d;
     653         8620 :    logic [3:0]  dec_i0_rs2_bypass_en_d;
     654              : 
     655      5412927 :    logic         dec_i0_alu_decode_d;
     656      3884730 :    logic         dec_i0_branch_d;
     657              : 
     658      5894275 :    logic         ifu_miss_state_idle;
     659          240 :    logic         dec_tlu_flush_noredir_r;
     660            2 :    logic         dec_tlu_flush_leak_one_r;
     661            8 :    logic         dec_tlu_flush_err_r;
     662      6017050 :    logic         ifu_i0_valid;
     663       468822 :    logic [31:0]  ifu_i0_instr;
     664         1321 :    logic [31:1]  ifu_i0_pc;
     665              : 
     666       674166 :    logic        exu_flush_final;
     667              : 
     668       227622 :    logic [31:1] exu_flush_path_final;
     669              : 
     670       413433 :    logic [31:0] exu_lsu_rs1_d;
     671        81510 :    logic [31:0] exu_lsu_rs2_d;
     672              : 
     673              : 
     674       624111 :    el2_lsu_pkt_t    lsu_p;
     675      5495334 :    logic             dec_qual_lsu_d;
     676              : 
     677      2284221 :    logic        dec_lsu_valid_raw_d;
     678       270506 :    logic [11:0] dec_lsu_offset_d;
     679              : 
     680        45313 :    logic [31:0]  lsu_result_m;
     681        36052 :    logic [31:0]  lsu_result_corr_r;     // This is the ECC corrected data going to RF
     682            4 :    logic         lsu_single_ecc_error_incr;     // Increment the ecc counter
     683            4 :    el2_lsu_error_pkt_t lsu_error_pkt_r;
     684            2 :    logic         lsu_imprecise_error_load_any;
     685            2 :    logic         lsu_imprecise_error_store_any;
     686          292 :    logic [31:0]  lsu_imprecise_error_addr_any;
     687        48822 :    logic         lsu_load_stall_any;       // This is for blocking loads
     688        59146 :    logic         lsu_store_stall_any;      // This is for blocking stores
     689      1347319 :    logic         lsu_idle_any;             // doesn't include DMA
     690      1346978 :    logic         lsu_active;               // lsu is active. used for clock
     691              : 
     692              : 
     693        24696 :    logic [31:1]  lsu_fir_addr;        // fast interrupt address
     694            0 :    logic [1:0]   lsu_fir_error;       // Error during fast interrupt lookup
     695              : 
     696              :    // Non-blocking loads
     697       881678 :    logic                                 lsu_nonblock_load_valid_m;
     698       505169 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_tag_m;
     699            0 :    logic                                 lsu_nonblock_load_inv_r;
     700       505166 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_inv_tag_r;
     701       920958 :    logic                                 lsu_nonblock_load_data_valid;
     702        36608 :    logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0]   lsu_nonblock_load_data_tag;
     703        71610 :    logic [31:0]                          lsu_nonblock_load_data;
     704              : 
     705        77308 :    logic        dec_csr_ren_d;
     706         8121 :    logic [31:0] dec_csr_rddata_d;
     707              : 
     708         3978 :    logic [31:0] exu_csr_rs1_x;
     709              : 
     710      6172115 :    logic        dec_tlu_i0_commit_cmt;
     711        59242 :    logic        dec_tlu_flush_lower_r;
     712        59242 :    logic        dec_tlu_flush_lower_wb;
     713        29690 :    logic        dec_tlu_i0_kill_writeb_r;     // I0 is flushed, don't writeback any results to arch state
     714        18868 :    logic        dec_tlu_fence_i_r;            // flush is a fence_i rfnpc, flush icache
     715              : 
     716        24762 :    logic [31:1] dec_tlu_flush_path_r;
     717            0 :    logic [31:0] dec_tlu_mrac_ff;        // CSR for memory region control
     718              : 
     719      5773132 :    logic        ifu_i0_pc4;
     720              : 
     721            0 :    el2_mul_pkt_t  mul_p;
     722              : 
     723        78134 :    el2_div_pkt_t  div_p;
     724         2628 :    logic           dec_div_cancel;
     725              : 
     726        24784 :    logic [31:0] exu_div_result;
     727       156860 :    logic exu_div_wren;
     728              : 
     729      6202516 :    logic dec_i0_decode_d;
     730              : 
     731              : 
     732       138997 :    logic [31:1] pred_correct_npc_x;
     733              : 
     734       782419 :    el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
     735              : 
     736        34482 :    el2_predict_pkt_t  exu_mp_pkt;
     737       300174 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_eghr;
     738       379109 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr;
     739       196218 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
     740       115620 :    logic [pt.BTB_BTAG_SIZE-1:0]          exu_mp_btag;
     741              : 
     742       367233 :    logic [pt.BHT_GHR_SIZE-1:0]  exu_i0_br_fghr_r;
     743      2721536 :    logic [1:0]  exu_i0_br_hist_r;
     744        26468 :    logic        exu_i0_br_error_r;
     745         9608 :    logic        exu_i0_br_start_error_r;
     746      3013126 :    logic        exu_i0_br_valid_r;
     747       410687 :    logic        exu_i0_br_mp_r;
     748      2382206 :    logic        exu_i0_br_middle_r;
     749              : 
     750      2111116 :    logic        exu_i0_br_way_r;
     751              : 
     752       187590 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
     753              : 
     754            0 :    logic        dma_dccm_req;
     755           66 :    logic        dma_iccm_req;
     756           12 :    logic [2:0]  dma_mem_tag;
     757            0 :    logic [31:0] dma_mem_addr;
     758            0 :    logic [2:0]  dma_mem_sz;
     759           22 :    logic        dma_mem_write;
     760           12 :    logic [63:0] dma_mem_wdata;
     761              : 
     762            0 :    logic        dccm_dma_rvalid;
     763            4 :    logic        dccm_dma_ecc_error;
     764           12 :    logic [2:0]  dccm_dma_rtag;
     765        39564 :    logic [63:0] dccm_dma_rdata;
     766            0 :    logic        iccm_dma_rvalid;
     767            4 :    logic        iccm_dma_ecc_error;
     768           12 :    logic [2:0]  iccm_dma_rtag;
     769            0 :    logic [63:0] iccm_dma_rdata;
     770              : 
     771            0 :    logic        dma_dccm_stall_any;       // Stall the ld/st in decode if asserted
     772           26 :    logic        dma_iccm_stall_any;       // Stall the fetch
     773      2233448 :    logic        dccm_ready;
     774       638312 :    logic        iccm_ready;
     775              : 
     776            0 :    logic        dma_pmu_dccm_read;
     777            0 :    logic        dma_pmu_dccm_write;
     778            0 :    logic        dma_pmu_any_read;
     779           66 :    logic        dma_pmu_any_write;
     780              : 
     781          208 :    logic        ifu_i0_icaf;
     782          274 :    logic [1:0]  ifu_i0_icaf_type;
     783              : 
     784              : 
     785           86 :    logic        ifu_i0_icaf_second;
     786            2 :    logic        ifu_i0_dbecc;
     787            0 :    logic        iccm_dma_sb_error;
     788              : 
     789       206097 :    el2_br_pkt_t i0_brp;
     790       651203 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
     791       631046 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
     792        21223 :    logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
     793              : 
     794            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
     795            0 :    logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index
     796              : 
     797              : 
     798       506496 :    el2_predict_pkt_t dec_i0_predict_p_d;
     799              : 
     800       631046 :    logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d;                // DEC predict fghr
     801       651203 :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d;     // DEC predict index
     802        21223 :    logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d;               // DEC predict branch tag
     803              : 
     804              :    // PIC ports
     805            8 :    logic                  picm_wren;
     806            2 :    logic                  picm_rden;
     807           10 :    logic                  picm_mken;
     808          316 :    logic [31:0]           picm_rdaddr;
     809          316 :    logic [31:0]           picm_wraddr;
     810        92728 :    logic [31:0]           picm_wr_data;
     811            0 :    logic [31:0]           picm_rd_data;
     812              : 
     813              :    // feature disable from mfdc
     814            0 :    logic  dec_tlu_external_ldfwd_disable; // disable external load forwarding
     815            0 :    logic  dec_tlu_bpred_disable;
     816            6 :    logic  dec_tlu_wb_coalescing_disable;
     817          324 :    logic  dec_tlu_sideeffect_posted_disable;
     818          347 :    logic [2:0] dec_tlu_dma_qos_prty;         // DMA QoS priority coming from MFDC [18:16]
     819              : 
     820              :    // clock gating overrides from mcgc
     821            2 :    logic  dec_tlu_misc_clk_override;
     822            2 :    logic  dec_tlu_ifu_clk_override;
     823            2 :    logic  dec_tlu_lsu_clk_override;
     824            2 :    logic  dec_tlu_bus_clk_override;
     825            2 :    logic  dec_tlu_pic_clk_override;
     826            2 :    logic  dec_tlu_dccm_clk_override;
     827            2 :    logic  dec_tlu_icm_clk_override;
     828              : 
     829          343 :    logic  dec_tlu_picio_clk_override;
     830              : 
     831              :    assign        dccm_clk_override = dec_tlu_dccm_clk_override;   // dccm memory
     832              :    assign        icm_clk_override = dec_tlu_icm_clk_override;    // icache/iccm memory
     833              : 
     834              :   // PMP Signals
     835            0 :   el2_pmp_cfg_pkt_t       pmp_pmpcfg  [pt.PMP_ENTRIES];
     836              :   logic [31:0]            pmp_pmpaddr [pt.PMP_ENTRIES];
     837       593687 :   logic [31:0]            pmp_chan_addr [3];
     838            0 :   el2_pmp_type_pkt_t      pmp_chan_type [3];
     839       137210 :   logic                   pmp_chan_err  [3];
     840              : 
     841          443 :   logic [31:1] ifu_pmp_addr;
     842          110 :   logic        ifu_pmp_error;
     843       593665 :   logic [31:0] lsu_pmp_addr_start;
     844       167064 :   logic        lsu_pmp_error_start;
     845       593691 :   logic [31:0] lsu_pmp_addr_end;
     846       167064 :   logic        lsu_pmp_error_end;
     847      1073287 :   logic        lsu_pmp_we;
     848      1424380 :   logic        lsu_pmp_re;
     849              : 
     850              :    // -----------------------DEBUG  START -------------------------------
     851              : 
     852           14 :    logic [31:0]            dbg_cmd_addr;              // the address of the debug command to used by the core
     853          124 :    logic [31:0]            dbg_cmd_wrdata;            // If the debug command is a write command, this has the data to be written to the CSR/GPR
     854         2562 :    logic                   dbg_cmd_valid;             // commad is being driven by the dbg module. One pulse. Only dirven when core_halted has been seen
     855          300 :    logic                   dbg_cmd_write;             // 1: write command; 0: read_command
     856         1456 :    logic [1:0]             dbg_cmd_type;              // 0:gpr 1:csr 2: memory
     857         1162 :    logic [1:0]             dbg_cmd_size;              // size of the abstract mem access debug command
     858            8 :    logic                   dbg_halt_req;              // Sticky signal indicating that the debug module wants to start the entering of debug mode ( start the halting sequence )
     859           10 :    logic                   dbg_resume_req;            // Sticky signal indicating that the debug module wants to resume from debug mode
     860          341 :    logic                   dbg_core_rst_l;            // Core reset from DM
     861              : 
     862         2562 :    logic                   core_dbg_cmd_done;         // Final muxed cmd done to debug
     863            4 :    logic                   core_dbg_cmd_fail;         // Final muxed cmd done to debug
     864       314097 :    logic [31:0]            core_dbg_rddata;           // Final muxed cmd done to debug
     865              : 
     866            4 :    logic                   dma_dbg_cmd_done;          // Abstarct memory command sent to dma is done
     867            4 :    logic                   dma_dbg_cmd_fail;          // Abstarct memory command sent to dma failed
     868            0 :    logic [31:0]            dma_dbg_rddata;            // Read data for abstract memory access
     869              : 
     870         2562 :    logic                   dbg_dma_bubble;            // Debug needs a bubble to send a valid
     871         2562 :    logic                   dma_dbg_ready;             // DMA is ready to accept debug request
     872              : 
     873       314097 :    logic [31:0]            dec_dbg_rddata;            // The core drives this data ( intercepts the pipe and sends it here )
     874         2558 :    logic                   dec_dbg_cmd_done;          // This will be treated like a valid signal
     875            0 :    logic                   dec_dbg_cmd_fail;          // Abstract command failed
     876          114 :    logic                   dec_tlu_mpc_halted_only;   // Only halted due to MPC
     877          126 :    logic                   dec_tlu_dbg_halted;        // The core has finished the queiscing sequence. Sticks this signal high
     878           10 :    logic                   dec_tlu_resume_ack;
     879          124 :    logic                   dec_tlu_debug_mode;        // Core is in debug mode
     880          168 :    logic                   dec_debug_wdata_rs1_d;
     881            0 :    logic                   dec_tlu_force_halt;        // halt has been forced
     882              : 
     883      6201901 :    logic [1:0]             dec_data_en;
     884      5996788 :    logic [1:0]             dec_ctl_en;
     885              : 
     886              :    // PMU Signals
     887       410687 :    logic                   exu_pmu_i0_br_misp;
     888      2910951 :    logic                   exu_pmu_i0_br_ataken;
     889      3495581 :    logic                   exu_pmu_i0_pc4;
     890              : 
     891       891818 :    logic                   lsu_pmu_load_external_m;
     892       813928 :    logic                   lsu_pmu_store_external_m;
     893        48802 :    logic                   lsu_pmu_misaligned_m;
     894      1675048 :    logic                   lsu_pmu_bus_trxn;
     895        36422 :    logic                   lsu_pmu_bus_misaligned;
     896            4 :    logic                   lsu_pmu_bus_error;
     897        67776 :    logic                   lsu_pmu_bus_busy;
     898              : 
     899       615052 :    logic                   ifu_pmu_fetch_stall;
     900      5895266 :    logic                   ifu_pmu_ic_miss;
     901       745228 :    logic                   ifu_pmu_ic_hit;
     902           10 :    logic                   ifu_pmu_bus_error;
     903      4468853 :    logic                   ifu_pmu_bus_busy;
     904     10364098 :    logic                   ifu_pmu_bus_trxn;
     905              : 
     906          451 :    logic                   active_state;
     907     69881769 :    logic                   free_clk;
     908     69881769 :    logic                   active_clk;
     909            2 :    logic                   dec_pause_state_cg;
     910              : 
     911            2 :    logic                   lsu_nonblock_load_data_error;
     912              : 
     913      1428506 :    logic [15:0]            ifu_i0_cinst;
     914              : 
     915              : // fast interrupt
     916            0 :    logic [31:2]            dec_tlu_meihap;
     917            0 :    logic                   dec_extint_stall;
     918              : 
     919      5525183 :    el2_trace_pkt_t  trace_rv_trace_pkt;
     920              : 
     921              : 
     922            4 :    logic                   lsu_fastint_stall_any;
     923              : 
     924            0 :    logic [7:0]  pic_claimid;
     925            0 :    logic [3:0]  pic_pl, dec_tlu_meicurpl, dec_tlu_meipt;
     926            0 :    logic        mexintpend;
     927            0 :    logic        mhwakeup;
     928              : 
     929           70 :    logic        dma_active;
     930              : 
     931              : 
     932            2 :    logic        pause_state;
     933          108 :    logic        halt_state;
     934              : 
     935      2091850 :    logic        dec_tlu_core_empty;
     936              : 
     937              :    assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
     938              : 
     939              :    assign halt_state = o_cpu_halt_status & ~(dma_active | lsu_active);
     940              : 
     941              : 
     942              :    assign active_state = (~(halt_state | pause_state) | dec_tlu_flush_lower_r | dec_tlu_flush_lower_wb)  | dec_tlu_misc_clk_override;
     943              : 
     944              :    rvoclkhdr free_cg2   ( .clk(clk), .en(1'b1),         .l1clk(free_l2clk), .* );
     945              :    rvoclkhdr active_cg2 ( .clk(clk), .en(active_state), .l1clk(active_l2clk), .* );
     946              : 
     947              : // all other clock headers are 1st level
     948              :    rvoclkhdr free_cg1   ( .clk(free_l2clk),     .en(1'b1), .l1clk(free_clk), .* );
     949              :    rvoclkhdr active_cg1 ( .clk(active_l2clk),   .en(1'b1), .l1clk(active_clk), .* );
     950              : 
     951              : 
     952              :    assign core_dbg_cmd_done = dma_dbg_cmd_done | dec_dbg_cmd_done;
     953              :    assign core_dbg_cmd_fail = dma_dbg_cmd_fail | dec_dbg_cmd_fail;
     954              :    assign core_dbg_rddata[31:0] = dma_dbg_cmd_done ? dma_dbg_rddata[31:0] : dec_dbg_rddata[31:0];
     955              : 
     956              :    el2_dbg #(.pt(pt)) dbg (
     957              :       .rst_l(core_rst_l),
     958              :       .clk(free_l2clk),
     959              :       .clk_override(dec_tlu_misc_clk_override),
     960              : 
     961              :       // AXI signals
     962              :       .sb_axi_awready(sb_axi_awready_int),
     963              :       .sb_axi_wready(sb_axi_wready_int),
     964              :       .sb_axi_bvalid(sb_axi_bvalid_int),
     965              :       .sb_axi_bresp(sb_axi_bresp_int[1:0]),
     966              : 
     967              :       .sb_axi_arready(sb_axi_arready_int),
     968              :       .sb_axi_rvalid(sb_axi_rvalid_int),
     969              :       .sb_axi_rdata(sb_axi_rdata_int[63:0]),
     970              :       .sb_axi_rresp(sb_axi_rresp_int[1:0]),
     971              :       .*
     972              :    );
     973              : 
     974              : `ifdef RV_ASSERT_ON
     975              :       assert_fetch_indbghalt: assert #0 (~(ifu.ifc_fetch_req_f & dec.tlu.dbg_tlu_halted_f & ~dec.tlu.dcsr_single_step_running)) else $display("ERROR: Fetching in dBG halt!");
     976              : `endif
     977              : 
     978              :    // -----------------   DEBUG END -----------------------------
     979              : 
     980              :    assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
     981              : 
     982              : `ifdef RV_USER_MODE
     983              : 
     984              :    // Operating privilege mode, 0 - machine, 1 - user
     985          864 :    logic priv_mode;
     986              :    // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
     987          960 :    logic priv_mode_eff;
     988              :    // Next privilege mode
     989          864 :    logic priv_mode_ns;
     990              : 
     991            2 :    el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
     992              : 
     993              : `endif
     994              : 
     995              :    // fetch
     996              :    el2_ifu #(.pt(pt)) ifu (
     997              :                             .clk(active_l2clk),
     998              :                             .rst_l(core_rst_l),
     999              :                             .dec_tlu_flush_err_wb       (dec_tlu_flush_err_r      ),
    1000              :                             .dec_tlu_flush_noredir_wb   (dec_tlu_flush_noredir_r  ),
    1001              :                             .dec_tlu_fence_i_wb         (dec_tlu_fence_i_r        ),
    1002              :                             .dec_tlu_flush_leak_one_wb  (dec_tlu_flush_leak_one_r ),
    1003              :                             .dec_tlu_flush_lower_wb     (dec_tlu_flush_lower_r    ),
    1004              : 
    1005              :                             // AXI signals
    1006              :                             .ifu_axi_arready(ifu_axi_arready_int),
    1007              :                             .ifu_axi_rvalid(ifu_axi_rvalid_int),
    1008              :                             .ifu_axi_rid(ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0]),
    1009              :                             .ifu_axi_rdata(ifu_axi_rdata_int[63:0]),
    1010              :                             .ifu_axi_rresp(ifu_axi_rresp_int[1:0]),
    1011              : 
    1012              :                             .*
    1013              :                             );
    1014              : 
    1015              : 
    1016              :    assign iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || ifu_iccm_dma_rd_ecc_single_err;
    1017              :    assign iccm_ecc_double_error = ifu_iccm_rd_ecc_double_err;
    1018              : 
    1019              :    el2_dec #(.pt(pt)) dec (
    1020              :                             .clk(active_l2clk),
    1021              :                             .dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),
    1022              :                             .rst_l(core_rst_l),
    1023              :                             .*
    1024              :                             );
    1025              : 
    1026              :    el2_exu #(.pt(pt)) exu (
    1027              :                             .clk(active_l2clk),
    1028              :                             .rst_l(core_rst_l),
    1029              :                             .*
    1030              :                             );
    1031              : 
    1032              :    el2_lsu #(.pt(pt)) lsu (
    1033              :                             .clk(active_l2clk),
    1034              :                             .rst_l(core_rst_l),
    1035              :                             .clk_override(dec_tlu_lsu_clk_override),
    1036              :                             .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r),
    1037              : 
    1038              :                             // AXI signals
    1039              :                             .lsu_axi_awready(lsu_axi_awready_int),
    1040              :                             .lsu_axi_wready(lsu_axi_wready_int),
    1041              :                             .lsu_axi_bvalid(lsu_axi_bvalid_int),
    1042              :                             .lsu_axi_bid(lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0]),
    1043              :                             .lsu_axi_bresp(lsu_axi_bresp_int[1:0]),
    1044              : 
    1045              :                             .lsu_axi_arready(lsu_axi_arready_int),
    1046              :                             .lsu_axi_rvalid(lsu_axi_rvalid_int),
    1047              :                             .lsu_axi_rid(lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0]),
    1048              :                             .lsu_axi_rdata(lsu_axi_rdata_int[63:0]),
    1049              :                             .lsu_axi_rresp(lsu_axi_rresp_int[1:0]),
    1050              :                             .lsu_axi_rlast(lsu_axi_rlast_int),
    1051              : 
    1052              :                             .*
    1053              : 
    1054              :                             );
    1055              : 
    1056              :    assign dccm_ecc_single_error = lsu_dccm_rd_ecc_single_err;
    1057              :    assign dccm_ecc_double_error = lsu_dccm_rd_ecc_double_err;
    1058              : 
    1059              :    el2_pic_ctrl  #(.pt(pt)) pic_ctrl_inst (
    1060              :                                             .clk(free_l2clk),
    1061              :                                             .clk_override(dec_tlu_pic_clk_override),
    1062              :                                             .io_clk_override(dec_tlu_picio_clk_override),
    1063              :                                             .picm_mken (picm_mken),
    1064              :                                             .extintsrc_req({extintsrc_req[pt.PIC_TOTAL_INT:1],1'b0}),
    1065              :                                             .pl(pic_pl[3:0]),
    1066              :                                             .claimid(pic_claimid[7:0]),
    1067              :                                             .meicurpl(dec_tlu_meicurpl[3:0]),
    1068              :                                             .meipt(dec_tlu_meipt[3:0]),
    1069              :                                             .rst_l(core_rst_l),
    1070              :                                             .*);
    1071              : 
    1072              :    el2_dma_ctrl #(.pt(pt)) dma_ctrl (
    1073              :                                       .clk(free_l2clk),
    1074              :                                       .rst_l(core_rst_l),
    1075              :                                       .clk_override(dec_tlu_misc_clk_override),
    1076              : 
    1077              :                                       // AXI signals
    1078              :                                       .dma_axi_awvalid(dma_axi_awvalid_int),
    1079              :                                       .dma_axi_awid(dma_axi_awid_int[pt.DMA_BUS_TAG-1:0]),
    1080              :                                       .dma_axi_awaddr(dma_axi_awaddr_int[31:0]),
    1081              :                                       .dma_axi_awsize(dma_axi_awsize_int[2:0]),
    1082              :                                       .dma_axi_wvalid(dma_axi_wvalid_int),
    1083              :                                       .dma_axi_wdata(dma_axi_wdata_int[63:0]),
    1084              :                                       .dma_axi_wstrb(dma_axi_wstrb_int[7:0]),
    1085              :                                       .dma_axi_bready(dma_axi_bready_int),
    1086              : 
    1087              :                                       .dma_axi_arvalid(dma_axi_arvalid_int),
    1088              :                                       .dma_axi_arid(dma_axi_arid_int[pt.DMA_BUS_TAG-1:0]),
    1089              :                                       .dma_axi_araddr(dma_axi_araddr_int[31:0]),
    1090              :                                       .dma_axi_arsize(dma_axi_arsize_int[2:0]),
    1091              :                                       .dma_axi_rready(dma_axi_rready_int),
    1092              : 
    1093              :                                       .*
    1094              :                                       );
    1095              : 
    1096              :   assign pmp_chan_addr[0] = {ifu_pmp_addr, 1'b0};
    1097              :   assign pmp_chan_type[0] = EXEC;
    1098              :   assign ifu_pmp_error    = pmp_chan_err[0];
    1099              :   assign pmp_chan_addr[1] = lsu_pmp_addr_start;
    1100              :   assign pmp_chan_type[1] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
    1101              :   assign lsu_pmp_error_start = pmp_chan_err[1];
    1102              :   assign pmp_chan_addr[2] = lsu_pmp_addr_end;
    1103              :   assign pmp_chan_type[2] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
    1104              :   assign lsu_pmp_error_end = pmp_chan_err[2];
    1105              : 
    1106              :   el2_pmp #(
    1107              :       .PMP_CHANNELS(3),
    1108              :       .pt(pt)
    1109              :   ) pmp (
    1110              :       .clk  (active_l2clk),
    1111              :       .rst_l(core_rst_l),
    1112              :       .*
    1113              :   );
    1114              : 
    1115              :    if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB
    1116              : 
    1117              :       // AXI4 -> AHB Gasket for LSU
    1118              :       axi4_to_ahb #(.pt(pt),
    1119              :                     .TAG(pt.LSU_BUS_TAG)) lsu_axi4_to_ahb (
    1120              : 
    1121              :          .clk(free_l2clk),
    1122              :          .free_clk(free_clk),
    1123              :          .rst_l(core_rst_l),
    1124              :          .clk_override(dec_tlu_bus_clk_override),
    1125              :          .bus_clk_en(lsu_bus_clk_en),
    1126              :          .dec_tlu_force_halt(dec_tlu_force_halt),
    1127              : 
    1128              :          // AXI Write Channels
    1129              :          .axi_awvalid(lsu_axi_awvalid),
    1130              :          .axi_awready(lsu_axi_awready_ahb),
    1131              :          .axi_awid(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]),
    1132              :          .axi_awaddr(lsu_axi_awaddr[31:0]),
    1133              :          .axi_awsize(lsu_axi_awsize[2:0]),
    1134              :          .axi_awprot(lsu_axi_awprot[2:0]),
    1135              : 
    1136              :          .axi_wvalid(lsu_axi_wvalid),
    1137              :          .axi_wready(lsu_axi_wready_ahb),
    1138              :          .axi_wdata(lsu_axi_wdata[63:0]),
    1139              :          .axi_wstrb(lsu_axi_wstrb[7:0]),
    1140              :          .axi_wlast(lsu_axi_wlast),
    1141              : 
    1142              :          .axi_bvalid(lsu_axi_bvalid_ahb),
    1143              :          .axi_bready(lsu_axi_bready),
    1144              :          .axi_bresp(lsu_axi_bresp_ahb[1:0]),
    1145              :          .axi_bid(lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0]),
    1146              : 
    1147              :          // AXI Read Channels
    1148              :          .axi_arvalid(lsu_axi_arvalid),
    1149              :          .axi_arready(lsu_axi_arready_ahb),
    1150              :          .axi_arid(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]),
    1151              :          .axi_araddr(lsu_axi_araddr[31:0]),
    1152              :          .axi_arsize(lsu_axi_arsize[2:0]),
    1153              :          .axi_arprot(lsu_axi_arprot[2:0]),
    1154              : 
    1155              :          .axi_rvalid(lsu_axi_rvalid_ahb),
    1156              :          .axi_rready(lsu_axi_rready),
    1157              :          .axi_rid(lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0]),
    1158              :          .axi_rdata(lsu_axi_rdata_ahb[63:0]),
    1159              :          .axi_rresp(lsu_axi_rresp_ahb[1:0]),
    1160              :          .axi_rlast(lsu_axi_rlast_ahb),
    1161              : 
    1162              :          // AHB-LITE signals
    1163              :          .ahb_haddr(lsu_haddr[31:0]),
    1164              :          .ahb_hburst(lsu_hburst),
    1165              :          .ahb_hmastlock(lsu_hmastlock),
    1166              :          .ahb_hprot(lsu_hprot[3:0]),
    1167              :          .ahb_hsize(lsu_hsize[2:0]),
    1168              :          .ahb_htrans(lsu_htrans[1:0]),
    1169              :          .ahb_hwrite(lsu_hwrite),
    1170              :          .ahb_hwdata(lsu_hwdata[63:0]),
    1171              : 
    1172              :          .ahb_hrdata(lsu_hrdata[63:0]),
    1173              :          .ahb_hready(lsu_hready),
    1174              :          .ahb_hresp(lsu_hresp),
    1175              : 
    1176              :          .*
    1177              :       );
    1178              : 
    1179              :       axi4_to_ahb #(.pt(pt),
    1180              :                     .TAG(pt.IFU_BUS_TAG)) ifu_axi4_to_ahb (
    1181              :          .clk(free_l2clk),
    1182              :          .free_clk(free_clk),
    1183              :          .rst_l(core_rst_l),
    1184              :          .clk_override(dec_tlu_bus_clk_override),
    1185              :          .bus_clk_en(ifu_bus_clk_en),
    1186              :          .dec_tlu_force_halt(dec_tlu_force_halt),
    1187              : 
    1188              :           // AHB-Lite signals
    1189              :          .ahb_haddr(haddr[31:0]),
    1190              :          .ahb_hburst(hburst),
    1191              :          .ahb_hmastlock(hmastlock),
    1192              :          .ahb_hprot(hprot[3:0]),
    1193              :          .ahb_hsize(hsize[2:0]),
    1194              :          .ahb_htrans(htrans[1:0]),
    1195              :          .ahb_hwrite(hwrite),
    1196              :          .ahb_hwdata(hwdata_nc[63:0]),
    1197              : 
    1198              :          .ahb_hrdata(hrdata[63:0]),
    1199              :          .ahb_hready(hready),
    1200              :          .ahb_hresp(hresp),
    1201              : 
    1202              :          // AXI Write Channels
    1203              :          .axi_awvalid(ifu_axi_awvalid),
    1204              :          .axi_awready(ifu_axi_awready_ahb),
    1205              :          .axi_awid(ifu_axi_awid[pt.IFU_BUS_TAG-1:0]),
    1206              :          .axi_awaddr(ifu_axi_awaddr[31:0]),
    1207              :          .axi_awsize(ifu_axi_awsize[2:0]),
    1208              :          .axi_awprot(ifu_axi_awprot[2:0]),
    1209              : 
    1210              :          .axi_wvalid(ifu_axi_wvalid),
    1211              :          .axi_wready(ifu_axi_wready_ahb),
    1212              :          .axi_wdata(ifu_axi_wdata[63:0]),
    1213              :          .axi_wstrb(ifu_axi_wstrb[7:0]),
    1214              :          .axi_wlast(ifu_axi_wlast),
    1215              : 
    1216              :          .axi_bvalid(ifu_axi_bvalid_ahb),
    1217              :          .axi_bready(1'b1),
    1218              :          .axi_bresp(ifu_axi_bresp_ahb[1:0]),
    1219              :          .axi_bid(ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0]),
    1220              : 
    1221              :          // AXI Read Channels
    1222              :          .axi_arvalid(ifu_axi_arvalid),
    1223              :          .axi_arready(ifu_axi_arready_ahb),
    1224              :          .axi_arid(ifu_axi_arid[pt.IFU_BUS_TAG-1:0]),
    1225              :          .axi_araddr(ifu_axi_araddr[31:0]),
    1226              :          .axi_arsize(ifu_axi_arsize[2:0]),
    1227              :          .axi_arprot(ifu_axi_arprot[2:0]),
    1228              : 
    1229              :          .axi_rvalid(ifu_axi_rvalid_ahb),
    1230              :          .axi_rready(ifu_axi_rready),
    1231              :          .axi_rid(ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0]),
    1232              :          .axi_rdata(ifu_axi_rdata_ahb[63:0]),
    1233              :          .axi_rresp(ifu_axi_rresp_ahb[1:0]),
    1234              :          .axi_rlast(ifu_axi_rlast_ahb),
    1235              :          .*
    1236              :       );
    1237              : 
    1238              :       // AXI4 -> AHB Gasket for System Bus
    1239              :       axi4_to_ahb #(.pt(pt),
    1240              :                     .TAG(pt.SB_BUS_TAG)) sb_axi4_to_ahb (
    1241              :          .clk(free_l2clk),
    1242              :          .free_clk(free_clk),
    1243              :          .rst_l(dbg_rst_l),
    1244              :          .clk_override(dec_tlu_bus_clk_override),
    1245              :          .bus_clk_en(dbg_bus_clk_en),
    1246              :          .dec_tlu_force_halt(1'b0),
    1247              : 
    1248              :          // AXI Write Channels
    1249              :          .axi_awvalid(sb_axi_awvalid),
    1250              :          .axi_awready(sb_axi_awready_ahb),
    1251              :          .axi_awid(sb_axi_awid[pt.SB_BUS_TAG-1:0]),
    1252              :          .axi_awaddr(sb_axi_awaddr[31:0]),
    1253              :          .axi_awsize(sb_axi_awsize[2:0]),
    1254              :          .axi_awprot(sb_axi_awprot[2:0]),
    1255              : 
    1256              :          .axi_wvalid(sb_axi_wvalid),
    1257              :          .axi_wready(sb_axi_wready_ahb),
    1258              :          .axi_wdata(sb_axi_wdata[63:0]),
    1259              :          .axi_wstrb(sb_axi_wstrb[7:0]),
    1260              :          .axi_wlast(sb_axi_wlast),
    1261              : 
    1262              :          .axi_bvalid(sb_axi_bvalid_ahb),
    1263              :          .axi_bready(sb_axi_bready),
    1264              :          .axi_bresp(sb_axi_bresp_ahb[1:0]),
    1265              :          .axi_bid(sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0]),
    1266              : 
    1267              :          // AXI Read Channels
    1268              :          .axi_arvalid(sb_axi_arvalid),
    1269              :          .axi_arready(sb_axi_arready_ahb),
    1270              :          .axi_arid(sb_axi_arid[pt.SB_BUS_TAG-1:0]),
    1271              :          .axi_araddr(sb_axi_araddr[31:0]),
    1272              :          .axi_arsize(sb_axi_arsize[2:0]),
    1273              :          .axi_arprot(sb_axi_arprot[2:0]),
    1274              : 
    1275              :          .axi_rvalid(sb_axi_rvalid_ahb),
    1276              :          .axi_rready(sb_axi_rready),
    1277              :          .axi_rid(sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0]),
    1278              :          .axi_rdata(sb_axi_rdata_ahb[63:0]),
    1279              :          .axi_rresp(sb_axi_rresp_ahb[1:0]),
    1280              :          .axi_rlast(sb_axi_rlast_ahb),
    1281              :          // AHB-LITE signals
    1282              :          .ahb_haddr(sb_haddr[31:0]),
    1283              :          .ahb_hburst(sb_hburst),
    1284              :          .ahb_hmastlock(sb_hmastlock),
    1285              :          .ahb_hprot(sb_hprot[3:0]),
    1286              :          .ahb_hsize(sb_hsize[2:0]),
    1287              :          .ahb_htrans(sb_htrans[1:0]),
    1288              :          .ahb_hwrite(sb_hwrite),
    1289              :          .ahb_hwdata(sb_hwdata[63:0]),
    1290              : 
    1291              :          .ahb_hrdata(sb_hrdata[63:0]),
    1292              :          .ahb_hready(sb_hready),
    1293              :          .ahb_hresp(sb_hresp),
    1294              : 
    1295              :          .*
    1296              :       );
    1297              : 
    1298              :       //AHB -> AXI4 Gasket for DMA
    1299              :       ahb_to_axi4 #(.pt(pt),
    1300              :                     .TAG(pt.DMA_BUS_TAG)) dma_ahb_to_axi4 (
    1301              :          .clk(free_l2clk),
    1302              :          .rst_l(core_rst_l),
    1303              :          .clk_override(dec_tlu_bus_clk_override),
    1304              :          .bus_clk_en(dma_bus_clk_en),
    1305              : 
    1306              :          // AXI Write Channels
    1307              :          .axi_awvalid(dma_axi_awvalid_ahb),
    1308              :          .axi_awready(dma_axi_awready),
    1309              :          .axi_awid(dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0]),
    1310              :          .axi_awaddr(dma_axi_awaddr_ahb[31:0]),
    1311              :          .axi_awsize(dma_axi_awsize_ahb[2:0]),
    1312              :          .axi_awprot(dma_axi_awprot_ahb[2:0]),
    1313              :          .axi_awlen(dma_axi_awlen_ahb[7:0]),
    1314              :          .axi_awburst(dma_axi_awburst_ahb[1:0]),
    1315              : 
    1316              :          .axi_wvalid(dma_axi_wvalid_ahb),
    1317              :          .axi_wready(dma_axi_wready),
    1318              :          .axi_wdata(dma_axi_wdata_ahb[63:0]),
    1319              :          .axi_wstrb(dma_axi_wstrb_ahb[7:0]),
    1320              :          .axi_wlast(dma_axi_wlast_ahb),
    1321              : 
    1322              :          .axi_bvalid(dma_axi_bvalid),
    1323              :          .axi_bready(dma_axi_bready_ahb),
    1324              :          .axi_bresp(dma_axi_bresp[1:0]),
    1325              :          .axi_bid(dma_axi_bid[pt.DMA_BUS_TAG-1:0]),
    1326              : 
    1327              :          // AXI Read Channels
    1328              :          .axi_arvalid(dma_axi_arvalid_ahb),
    1329              :          .axi_arready(dma_axi_arready),
    1330              :          .axi_arid(dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0]),
    1331              :          .axi_araddr(dma_axi_araddr_ahb[31:0]),
    1332              :          .axi_arsize(dma_axi_arsize_ahb[2:0]),
    1333              :          .axi_arprot(dma_axi_arprot_ahb[2:0]),
    1334              :          .axi_arlen(dma_axi_arlen_ahb[7:0]),
    1335              :          .axi_arburst(dma_axi_arburst_ahb[1:0]),
    1336              : 
    1337              :          .axi_rvalid(dma_axi_rvalid),
    1338              :          .axi_rready(dma_axi_rready_ahb),
    1339              :          .axi_rid(dma_axi_rid[pt.DMA_BUS_TAG-1:0]),
    1340              :          .axi_rdata(dma_axi_rdata[63:0]),
    1341              :          .axi_rresp(dma_axi_rresp[1:0]),
    1342              : 
    1343              :           // AHB signals
    1344              :          .ahb_haddr(dma_haddr[31:0]),
    1345              :          .ahb_hburst(dma_hburst),
    1346              :          .ahb_hmastlock(dma_hmastlock),
    1347              :          .ahb_hprot(dma_hprot[3:0]),
    1348              :          .ahb_hsize(dma_hsize[2:0]),
    1349              :          .ahb_htrans(dma_htrans[1:0]),
    1350              :          .ahb_hwrite(dma_hwrite),
    1351              :          .ahb_hwdata(dma_hwdata[63:0]),
    1352              : 
    1353              :          .ahb_hrdata(dma_hrdata[63:0]),
    1354              :          .ahb_hreadyout(dma_hreadyout),
    1355              :          .ahb_hresp(dma_hresp),
    1356              :          .ahb_hreadyin(dma_hreadyin),
    1357              :          .ahb_hsel(dma_hsel),
    1358              :          .*
    1359              :       );
    1360              : 
    1361              :    end
    1362              : 
    1363              :    // Drive the final AXI inputs
    1364              :    assign lsu_axi_awready_int                 = pt.BUILD_AHB_LITE ? lsu_axi_awready_ahb : lsu_axi_awready;
    1365              :    assign lsu_axi_wready_int                  = pt.BUILD_AHB_LITE ? lsu_axi_wready_ahb : lsu_axi_wready;
    1366              :    assign lsu_axi_bvalid_int                  = pt.BUILD_AHB_LITE ? lsu_axi_bvalid_ahb : lsu_axi_bvalid;
    1367              :    assign lsu_axi_bready_int                  = pt.BUILD_AHB_LITE ? lsu_axi_bready_ahb : lsu_axi_bready;
    1368              :    assign lsu_axi_bresp_int[1:0]              = pt.BUILD_AHB_LITE ? lsu_axi_bresp_ahb[1:0] : lsu_axi_bresp[1:0];
    1369              :    assign lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_bid[pt.LSU_BUS_TAG-1:0];
    1370              :    assign lsu_axi_arready_int                 = pt.BUILD_AHB_LITE ? lsu_axi_arready_ahb : lsu_axi_arready;
    1371              :    assign lsu_axi_rvalid_int                  = pt.BUILD_AHB_LITE ? lsu_axi_rvalid_ahb : lsu_axi_rvalid;
    1372              :    assign lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_rid[pt.LSU_BUS_TAG-1:0];
    1373              :    assign lsu_axi_rdata_int[63:0]             = pt.BUILD_AHB_LITE ? lsu_axi_rdata_ahb[63:0] : lsu_axi_rdata[63:0];
    1374              :    assign lsu_axi_rresp_int[1:0]              = pt.BUILD_AHB_LITE ? lsu_axi_rresp_ahb[1:0] : lsu_axi_rresp[1:0];
    1375              :    assign lsu_axi_rlast_int                   = pt.BUILD_AHB_LITE ? lsu_axi_rlast_ahb : lsu_axi_rlast;
    1376              : 
    1377              :    assign ifu_axi_awready_int                 = pt.BUILD_AHB_LITE ? ifu_axi_awready_ahb : ifu_axi_awready;
    1378              :    assign ifu_axi_wready_int                  = pt.BUILD_AHB_LITE ? ifu_axi_wready_ahb : ifu_axi_wready;
    1379              :    assign ifu_axi_bvalid_int                  = pt.BUILD_AHB_LITE ? ifu_axi_bvalid_ahb : ifu_axi_bvalid;
    1380              :    assign ifu_axi_bready_int                  = pt.BUILD_AHB_LITE ? ifu_axi_bready_ahb : ifu_axi_bready;
    1381              :    assign ifu_axi_bresp_int[1:0]              = pt.BUILD_AHB_LITE ? ifu_axi_bresp_ahb[1:0] : ifu_axi_bresp[1:0];
    1382              :    assign ifu_axi_bid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_bid[pt.IFU_BUS_TAG-1:0];
    1383              :    assign ifu_axi_arready_int                 = pt.BUILD_AHB_LITE ? ifu_axi_arready_ahb : ifu_axi_arready;
    1384              :    assign ifu_axi_rvalid_int                  = pt.BUILD_AHB_LITE ? ifu_axi_rvalid_ahb : ifu_axi_rvalid;
    1385              :    assign ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_rid[pt.IFU_BUS_TAG-1:0];
    1386              :    assign ifu_axi_rdata_int[63:0]             = pt.BUILD_AHB_LITE ? ifu_axi_rdata_ahb[63:0] : ifu_axi_rdata[63:0];
    1387              :    assign ifu_axi_rresp_int[1:0]              = pt.BUILD_AHB_LITE ? ifu_axi_rresp_ahb[1:0] : ifu_axi_rresp[1:0];
    1388              :    assign ifu_axi_rlast_int                   = pt.BUILD_AHB_LITE ? ifu_axi_rlast_ahb : ifu_axi_rlast;
    1389              : 
    1390              :    assign sb_axi_awready_int                  = pt.BUILD_AHB_LITE ? sb_axi_awready_ahb : sb_axi_awready;
    1391              :    assign sb_axi_wready_int                   = pt.BUILD_AHB_LITE ? sb_axi_wready_ahb : sb_axi_wready;
    1392              :    assign sb_axi_bvalid_int                   = pt.BUILD_AHB_LITE ? sb_axi_bvalid_ahb : sb_axi_bvalid;
    1393              :    assign sb_axi_bready_int                   = pt.BUILD_AHB_LITE ? sb_axi_bready_ahb : sb_axi_bready;
    1394              :    assign sb_axi_bresp_int[1:0]               = pt.BUILD_AHB_LITE ? sb_axi_bresp_ahb[1:0] : sb_axi_bresp[1:0];
    1395              :    assign sb_axi_bid_int[pt.SB_BUS_TAG-1:0]   = pt.BUILD_AHB_LITE ? sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_bid[pt.SB_BUS_TAG-1:0];
    1396              :    assign sb_axi_arready_int                  = pt.BUILD_AHB_LITE ? sb_axi_arready_ahb : sb_axi_arready;
    1397              :    assign sb_axi_rvalid_int                   = pt.BUILD_AHB_LITE ? sb_axi_rvalid_ahb : sb_axi_rvalid;
    1398              :    assign sb_axi_rid_int[pt.SB_BUS_TAG-1:0]   = pt.BUILD_AHB_LITE ? sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_rid[pt.SB_BUS_TAG-1:0];
    1399              :    assign sb_axi_rdata_int[63:0]              = pt.BUILD_AHB_LITE ? sb_axi_rdata_ahb[63:0] : sb_axi_rdata[63:0];
    1400              :    assign sb_axi_rresp_int[1:0]               = pt.BUILD_AHB_LITE ? sb_axi_rresp_ahb[1:0] : sb_axi_rresp[1:0];
    1401              :    assign sb_axi_rlast_int                    = pt.BUILD_AHB_LITE ? sb_axi_rlast_ahb : sb_axi_rlast;
    1402              : 
    1403              :    assign dma_axi_awvalid_int                  = pt.BUILD_AHB_LITE ? dma_axi_awvalid_ahb : dma_axi_awvalid;
    1404              :    assign dma_axi_awid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_awid[pt.DMA_BUS_TAG-1:0];
    1405              :    assign dma_axi_awaddr_int[31:0]             = pt.BUILD_AHB_LITE ? dma_axi_awaddr_ahb[31:0] : dma_axi_awaddr[31:0];
    1406              :    assign dma_axi_awsize_int[2:0]              = pt.BUILD_AHB_LITE ? dma_axi_awsize_ahb[2:0] : dma_axi_awsize[2:0];
    1407              :    assign dma_axi_awprot_int[2:0]              = pt.BUILD_AHB_LITE ? dma_axi_awprot_ahb[2:0] : dma_axi_awprot[2:0];
    1408              :    assign dma_axi_awlen_int[7:0]               = pt.BUILD_AHB_LITE ? dma_axi_awlen_ahb[7:0] : dma_axi_awlen[7:0];
    1409              :    assign dma_axi_awburst_int[1:0]             = pt.BUILD_AHB_LITE ? dma_axi_awburst_ahb[1:0] : dma_axi_awburst[1:0];
    1410              :    assign dma_axi_wvalid_int                   = pt.BUILD_AHB_LITE ? dma_axi_wvalid_ahb : dma_axi_wvalid;
    1411              :    assign dma_axi_wdata_int[63:0]              = pt.BUILD_AHB_LITE ? dma_axi_wdata_ahb[63:0] : dma_axi_wdata;
    1412              :    assign dma_axi_wstrb_int[7:0]               = pt.BUILD_AHB_LITE ? dma_axi_wstrb_ahb[7:0] : dma_axi_wstrb[7:0];
    1413              :    assign dma_axi_wlast_int                    = pt.BUILD_AHB_LITE ? dma_axi_wlast_ahb : dma_axi_wlast;
    1414              :    assign dma_axi_bready_int                   = pt.BUILD_AHB_LITE ? dma_axi_bready_ahb : dma_axi_bready;
    1415              :    assign dma_axi_arvalid_int                  = pt.BUILD_AHB_LITE ? dma_axi_arvalid_ahb : dma_axi_arvalid;
    1416              :    assign dma_axi_arid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_arid[pt.DMA_BUS_TAG-1:0];
    1417              :    assign dma_axi_araddr_int[31:0]             = pt.BUILD_AHB_LITE ? dma_axi_araddr_ahb[31:0] : dma_axi_araddr[31:0];
    1418              :    assign dma_axi_arsize_int[2:0]              = pt.BUILD_AHB_LITE ? dma_axi_arsize_ahb[2:0] : dma_axi_arsize[2:0];
    1419              :    assign dma_axi_arprot_int[2:0]              = pt.BUILD_AHB_LITE ? dma_axi_arprot_ahb[2:0] : dma_axi_arprot[2:0];
    1420              :    assign dma_axi_arlen_int[7:0]               = pt.BUILD_AHB_LITE ? dma_axi_arlen_ahb[7:0] : dma_axi_arlen[7:0];
    1421              :    assign dma_axi_arburst_int[1:0]             = pt.BUILD_AHB_LITE ? dma_axi_arburst_ahb[1:0] : dma_axi_arburst[1:0];
    1422              :    assign dma_axi_rready_int                   = pt.BUILD_AHB_LITE ? dma_axi_rready_ahb : dma_axi_rready;
    1423              : 
    1424              : 
    1425              : if  (pt.BUILD_AHB_LITE == 1) begin
    1426              : `ifdef RV_ASSERT_ON
    1427              :    property ahb_trxn_aligned;
    1428              :      @(posedge clk) disable iff(~rst_l) (lsu_htrans[1:0] != 2'b0)  |-> ((lsu_hsize[2:0] == 3'h0)                              |
    1429              :                                                                         ((lsu_hsize[2:0] == 3'h1) & (lsu_haddr[0] == 1'b0))   |
    1430              :                                                                         ((lsu_hsize[2:0] == 3'h2) & (lsu_haddr[1:0] == 2'b0)) |
    1431              :                                                                         ((lsu_hsize[2:0] == 3'h3) & (lsu_haddr[2:0] == 3'b0)));
    1432              :    endproperty
    1433              :    assert_ahb_trxn_aligned: assert property (ahb_trxn_aligned) else
    1434              :      $display("Assertion ahb_trxn_aligned failed: lsu_htrans=2'h%h, lsu_hsize=3'h%h, lsu_haddr=32'h%h",lsu_htrans[1:0], lsu_hsize[2:0], lsu_haddr[31:0]);
    1435              : 
    1436              :    property dma_trxn_aligned;
    1437              :      @(posedge clk) disable iff(~rst_l) (dma_htrans[1:0] != 2'b0)  |-> ((dma_hsize[2:0] == 3'h0)                              |
    1438              :                                                                         ((dma_hsize[2:0] == 3'h1) & (dma_haddr[0] == 1'b0))   |
    1439              :                                                                         ((dma_hsize[2:0] == 3'h2) & (dma_haddr[1:0] == 2'b0)) |
    1440              :                                                                         ((dma_hsize[2:0] == 3'h3) & (dma_haddr[2:0] == 3'b0)));
    1441              :    endproperty
    1442              : 
    1443              : 
    1444              : `endif
    1445              :    end // if (pt.BUILD_AHB_LITE == 1)
    1446              : 
    1447              : 
    1448              :       // unpack packet
    1449              :       // also need retires_p==3
    1450              : 
    1451              :       assign trace_rv_i_insn_ip[31:0]     = trace_rv_trace_pkt.trace_rv_i_insn_ip[31:0];
    1452              : 
    1453              :       assign trace_rv_i_address_ip[31:0]  = trace_rv_trace_pkt.trace_rv_i_address_ip[31:0];
    1454              : 
    1455              :       assign trace_rv_i_valid_ip     = trace_rv_trace_pkt.trace_rv_i_valid_ip;
    1456              : 
    1457              :       assign trace_rv_i_exception_ip = trace_rv_trace_pkt.trace_rv_i_exception_ip;
    1458              : 
    1459              :       assign trace_rv_i_ecause_ip[4:0]    = trace_rv_trace_pkt.trace_rv_i_ecause_ip[4:0];
    1460              : 
    1461              :       assign trace_rv_i_interrupt_ip = trace_rv_trace_pkt.trace_rv_i_interrupt_ip;
    1462              : 
    1463              :       assign trace_rv_i_tval_ip[31:0]     = trace_rv_trace_pkt.trace_rv_i_tval_ip[31:0];
    1464              : 
    1465              : 
    1466              : 
    1467              : endmodule // el2_veer
    1468              :