Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : // Copyright (c) 2023 Antmicro <www.antmicro.com>
4 : //
5 : // Licensed under the Apache License, Version 2.0 (the "License");
6 : // you may not use this file except in compliance with the License.
7 : // You may obtain a copy of the License at
8 : //
9 : // http://www.apache.org/licenses/LICENSE-2.0
10 : //
11 : // Unless required by applicable law or agreed to in writing, software
12 : // distributed under the License is distributed on an "AS IS" BASIS,
13 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 : // See the License for the specific language governing permissions and
15 : // limitations under the License.
16 :
17 : //********************************************************************************
18 : // $Id$
19 : //
20 : // Function: Top wrapper file with el2_veer/mem instantiated inside
21 : // Comments:
22 : //
23 : //********************************************************************************
24 : module el2_veer_wrapper
25 : import el2_pkg::*;
26 : #(
27 : `include "el2_param.vh"
28 : )
29 : (
30 61045677 : input logic clk,
31 316 : input logic rst_l,
32 316 : input logic dbg_rst_l,
33 0 : input logic [31:1] rst_vec,
34 16 : input logic nmi_int,
35 0 : input logic [31:1] nmi_vec,
36 0 : input logic [31:1] jtag_id,
37 :
38 :
39 572576 : output logic [31:0] trace_rv_i_insn_ip,
40 308 : output logic [31:0] trace_rv_i_address_ip,
41 6090692 : output logic trace_rv_i_valid_ip,
42 5114 : output logic trace_rv_i_exception_ip,
43 0 : output logic [4:0] trace_rv_i_ecause_ip,
44 22 : output logic trace_rv_i_interrupt_ip,
45 52 : output logic [31:0] trace_rv_i_tval_ip,
46 :
47 : // Bus signals
48 : `ifdef RV_BUILD_AXI4
49 : //-------------------------- LSU AXI signals--------------------------
50 : // AXI Write Channels
51 650677 : output logic lsu_axi_awvalid,
52 660317 : input logic lsu_axi_awready,
53 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
54 391 : output logic [31:0] lsu_axi_awaddr,
55 297 : output logic [3:0] lsu_axi_awregion,
56 0 : output logic [7:0] lsu_axi_awlen,
57 0 : output logic [2:0] lsu_axi_awsize,
58 0 : output logic [1:0] lsu_axi_awburst,
59 0 : output logic lsu_axi_awlock,
60 1731 : output logic [3:0] lsu_axi_awcache,
61 0 : output logic [2:0] lsu_axi_awprot,
62 0 : output logic [3:0] lsu_axi_awqos,
63 :
64 650677 : output logic lsu_axi_wvalid,
65 660317 : input logic lsu_axi_wready,
66 29763 : output logic [63:0] lsu_axi_wdata,
67 185562 : output logic [7:0] lsu_axi_wstrb,
68 299 : output logic lsu_axi_wlast,
69 :
70 660078 : input logic lsu_axi_bvalid,
71 299 : output logic lsu_axi_bready,
72 0 : input logic [1:0] lsu_axi_bresp,
73 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
74 :
75 : // AXI Read Channels
76 630058 : output logic lsu_axi_arvalid,
77 672407 : input logic lsu_axi_arready,
78 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
79 391 : output logic [31:0] lsu_axi_araddr,
80 297 : output logic [3:0] lsu_axi_arregion,
81 0 : output logic [7:0] lsu_axi_arlen,
82 0 : output logic [2:0] lsu_axi_arsize,
83 0 : output logic [1:0] lsu_axi_arburst,
84 0 : output logic lsu_axi_arlock,
85 1731 : output logic [3:0] lsu_axi_arcache,
86 0 : output logic [2:0] lsu_axi_arprot,
87 0 : output logic [3:0] lsu_axi_arqos,
88 :
89 672110 : input logic lsu_axi_rvalid,
90 299 : output logic lsu_axi_rready,
91 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
92 26474 : input logic [63:0] lsu_axi_rdata,
93 0 : input logic [1:0] lsu_axi_rresp,
94 672118 : input logic lsu_axi_rlast,
95 :
96 : //-------------------------- IFU AXI signals--------------------------
97 : // AXI Write Channels
98 0 : output logic ifu_axi_awvalid,
99 0 : input logic ifu_axi_awready,
100 0 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
101 0 : output logic [31:0] ifu_axi_awaddr,
102 0 : output logic [3:0] ifu_axi_awregion,
103 0 : output logic [7:0] ifu_axi_awlen,
104 0 : output logic [2:0] ifu_axi_awsize,
105 0 : output logic [1:0] ifu_axi_awburst,
106 0 : output logic ifu_axi_awlock,
107 0 : output logic [3:0] ifu_axi_awcache,
108 0 : output logic [2:0] ifu_axi_awprot,
109 0 : output logic [3:0] ifu_axi_awqos,
110 :
111 0 : output logic ifu_axi_wvalid,
112 0 : input logic ifu_axi_wready,
113 0 : output logic [63:0] ifu_axi_wdata,
114 0 : output logic [7:0] ifu_axi_wstrb,
115 0 : output logic ifu_axi_wlast,
116 :
117 0 : input logic ifu_axi_bvalid,
118 0 : output logic ifu_axi_bready,
119 0 : input logic [1:0] ifu_axi_bresp,
120 0 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
121 :
122 : // AXI Read Channels
123 4406360 : output logic ifu_axi_arvalid,
124 8831737 : input logic ifu_axi_arready,
125 2711742 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
126 1918330 : output logic [31:0] ifu_axi_araddr,
127 300 : output logic [3:0] ifu_axi_arregion,
128 0 : output logic [7:0] ifu_axi_arlen,
129 0 : output logic [2:0] ifu_axi_arsize,
130 0 : output logic [1:0] ifu_axi_arburst,
131 0 : output logic ifu_axi_arlock,
132 299 : output logic [3:0] ifu_axi_arcache,
133 299 : output logic [2:0] ifu_axi_arprot,
134 0 : output logic [3:0] ifu_axi_arqos,
135 :
136 8831439 : input logic ifu_axi_rvalid,
137 299 : output logic ifu_axi_rready,
138 888509 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
139 734885 : input logic [63:0] ifu_axi_rdata,
140 0 : input logic [1:0] ifu_axi_rresp,
141 8831439 : input logic ifu_axi_rlast,
142 :
143 : //-------------------------- SB AXI signals--------------------------
144 : // AXI Write Channels
145 10 : output logic sb_axi_awvalid,
146 10 : input logic sb_axi_awready,
147 0 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
148 2 : output logic [31:0] sb_axi_awaddr,
149 2 : output logic [3:0] sb_axi_awregion,
150 0 : output logic [7:0] sb_axi_awlen,
151 0 : output logic [2:0] sb_axi_awsize,
152 0 : output logic [1:0] sb_axi_awburst,
153 0 : output logic sb_axi_awlock,
154 299 : output logic [3:0] sb_axi_awcache,
155 0 : output logic [2:0] sb_axi_awprot,
156 0 : output logic [3:0] sb_axi_awqos,
157 :
158 10 : output logic sb_axi_wvalid,
159 10 : input logic sb_axi_wready,
160 3 : output logic [63:0] sb_axi_wdata,
161 12 : output logic [7:0] sb_axi_wstrb,
162 299 : output logic sb_axi_wlast,
163 :
164 10 : input logic sb_axi_bvalid,
165 299 : output logic sb_axi_bready,
166 0 : input logic [1:0] sb_axi_bresp,
167 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
168 :
169 : // AXI Read Channels
170 8 : output logic sb_axi_arvalid,
171 8 : input logic sb_axi_arready,
172 0 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
173 2 : output logic [31:0] sb_axi_araddr,
174 2 : output logic [3:0] sb_axi_arregion,
175 0 : output logic [7:0] sb_axi_arlen,
176 0 : output logic [2:0] sb_axi_arsize,
177 0 : output logic [1:0] sb_axi_arburst,
178 0 : output logic sb_axi_arlock,
179 0 : output logic [3:0] sb_axi_arcache,
180 0 : output logic [2:0] sb_axi_arprot,
181 0 : output logic [3:0] sb_axi_arqos,
182 :
183 8 : input logic sb_axi_rvalid,
184 299 : output logic sb_axi_rready,
185 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
186 1 : input logic [63:0] sb_axi_rdata,
187 0 : input logic [1:0] sb_axi_rresp,
188 8 : input logic sb_axi_rlast,
189 :
190 : //-------------------------- DMA AXI signals--------------------------
191 : // AXI Write Channels
192 66 : input logic dma_axi_awvalid,
193 299 : output logic dma_axi_awready,
194 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
195 391 : input logic [31:0] dma_axi_awaddr,
196 0 : input logic [2:0] dma_axi_awsize,
197 0 : input logic [2:0] dma_axi_awprot,
198 0 : input logic [7:0] dma_axi_awlen,
199 0 : input logic [1:0] dma_axi_awburst,
200 :
201 :
202 66 : input logic dma_axi_wvalid,
203 299 : output logic dma_axi_wready,
204 29763 : input logic [63:0] dma_axi_wdata,
205 185562 : input logic [7:0] dma_axi_wstrb,
206 298 : input logic dma_axi_wlast,
207 :
208 66 : output logic dma_axi_bvalid,
209 66 : input logic dma_axi_bready,
210 0 : output logic [1:0] dma_axi_bresp,
211 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
212 :
213 : // AXI Read Channels
214 0 : input logic dma_axi_arvalid,
215 299 : output logic dma_axi_arready,
216 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
217 391 : input logic [31:0] dma_axi_araddr,
218 0 : input logic [2:0] dma_axi_arsize,
219 0 : input logic [2:0] dma_axi_arprot,
220 0 : input logic [7:0] dma_axi_arlen,
221 0 : input logic [1:0] dma_axi_arburst,
222 :
223 0 : output logic dma_axi_rvalid,
224 0 : input logic dma_axi_rready,
225 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
226 12 : output logic [63:0] dma_axi_rdata,
227 0 : output logic [1:0] dma_axi_rresp,
228 299 : output logic dma_axi_rlast,
229 : `endif
230 :
231 : `ifdef RV_BUILD_AHB_LITE
232 : //// AHB LITE BUS
233 15 : output logic [31:0] haddr,
234 0 : output logic [2:0] hburst,
235 0 : output logic hmastlock,
236 0 : output logic [3:0] hprot,
237 0 : output logic [2:0] hsize,
238 1413789 : output logic [1:0] htrans,
239 0 : output logic hwrite,
240 :
241 238151 : input logic [63:0] hrdata,
242 18 : input logic hready,
243 0 : input logic hresp,
244 :
245 : // LSU AHB Master
246 9 : output logic [31:0] lsu_haddr,
247 0 : output logic [2:0] lsu_hburst,
248 0 : output logic lsu_hmastlock,
249 0 : output logic [3:0] lsu_hprot,
250 0 : output logic [2:0] lsu_hsize,
251 434682 : output logic [1:0] lsu_htrans,
252 85537 : output logic lsu_hwrite,
253 5246 : output logic [63:0] lsu_hwdata,
254 :
255 2286 : input logic [63:0] lsu_hrdata,
256 18 : input logic lsu_hready,
257 0 : input logic lsu_hresp,
258 : // Debug Syster Bus AHB
259 2 : output logic [31:0] sb_haddr,
260 0 : output logic [2:0] sb_hburst,
261 0 : output logic sb_hmastlock,
262 0 : output logic [3:0] sb_hprot,
263 0 : output logic [2:0] sb_hsize,
264 18 : output logic [1:0] sb_htrans,
265 7 : output logic sb_hwrite,
266 3 : output logic [63:0] sb_hwdata,
267 :
268 4 : input logic [63:0] sb_hrdata,
269 1 : input logic sb_hready,
270 0 : input logic sb_hresp,
271 :
272 : // DMA Slave
273 18 : input logic dma_hsel,
274 0 : input logic [31:0] dma_haddr,
275 0 : input logic [2:0] dma_hburst,
276 0 : input logic dma_hmastlock,
277 0 : input logic [3:0] dma_hprot,
278 0 : input logic [2:0] dma_hsize,
279 0 : input logic [1:0] dma_htrans,
280 0 : input logic dma_hwrite,
281 0 : input logic [63:0] dma_hwdata,
282 18 : input logic dma_hreadyin,
283 :
284 0 : output logic [63:0] dma_hrdata,
285 18 : output logic dma_hreadyout,
286 0 : output logic dma_hresp,
287 : `endif
288 : // clk ratio signals
289 316 : input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
290 316 : input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
291 316 : input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
292 316 : input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
293 :
294 : // ICCM/DCCM ECC status
295 8 : output logic iccm_ecc_single_error,
296 4 : output logic iccm_ecc_double_error,
297 4 : output logic dccm_ecc_single_error,
298 4 : output logic dccm_ecc_double_error,
299 :
300 : // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not)
301 :
302 0 : input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
303 0 : input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
304 :
305 12 : input logic timer_int,
306 14 : input logic soft_int,
307 0 : input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
308 :
309 340148 : output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
310 514626 : output logic dec_tlu_perfcnt1,
311 312914 : output logic dec_tlu_perfcnt2,
312 48468 : output logic dec_tlu_perfcnt3,
313 :
314 : // ports added by the soc team
315 27812 : input logic jtag_tck, // JTAG clk
316 1472 : input logic jtag_tms, // JTAG TMS
317 1576 : input logic jtag_tdi, // JTAG tdi
318 2 : input logic jtag_trst_n, // JTAG Reset
319 2336 : output logic jtag_tdo, // JTAG TDO
320 732 : output logic jtag_tdoEn, // JTAG Test Data Output enable
321 :
322 0 : input logic [31:4] core_id,
323 :
324 : // Memory Export Interface
325 : el2_mem_if.veer_sram_src el2_mem_export,
326 :
327 : // external MPC halt/run interface
328 0 : input logic mpc_debug_halt_req, // Async halt request
329 316 : input logic mpc_debug_run_req, // Async run request
330 316 : input logic mpc_reset_run_req, // Run/halt after reset
331 0 : output logic mpc_debug_halt_ack, // Halt ack
332 316 : output logic mpc_debug_run_ack, // Run ack
333 0 : output logic debug_brkpt_status, // debug breakpoint
334 :
335 0 : input logic i_cpu_halt_req, // Async halt req to CPU
336 0 : output logic o_cpu_halt_ack, // core response to halt
337 0 : output logic o_cpu_halt_status, // 1'b1 indicates core is halted
338 0 : output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
339 0 : input logic i_cpu_run_req, // Async restart req to CPU
340 0 : output logic o_cpu_run_ack, // Core response to run req
341 0 : input logic scan_mode, // To enable scan mode
342 0 : input logic mbist_mode, // to enable mbist
343 :
344 : // DMI port for uncore
345 0 : input logic dmi_uncore_enable,
346 0 : output logic dmi_uncore_en,
347 0 : output logic dmi_uncore_wr_en,
348 0 : output logic [ 6:0] dmi_uncore_addr,
349 20 : output logic [31:0] dmi_uncore_wdata,
350 0 : input logic [31:0] dmi_uncore_rdata
351 : );
352 :
353 61045677 : logic active_l2clk;
354 61045677 : logic free_l2clk;
355 :
356 : // DCCM ports
357 262892 : logic dccm_wren;
358 561000 : logic dccm_rden;
359 18811 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo;
360 18811 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi;
361 470114 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo;
362 676449 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi;
363 5374 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo;
364 5374 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi;
365 :
366 47172 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;
367 47172 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;
368 :
369 : // PIC ports
370 :
371 : // Icache & Itag ports
372 326 : logic [31:1] ic_rw_addr;
373 10432 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en ; // Which way to write
374 680092 : logic ic_rd_en ;
375 :
376 :
377 255918 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid; // Valid from the I$ tag valid outside (in flops).
378 :
379 109586 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit; // ic_rd_hit[3:0]
380 0 : logic ic_tag_perr; // Ic tag parity error
381 :
382 0 : logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr; // Read/Write addresss to the Icache.
383 0 : logic ic_debug_rd_en; // Icache debug rd
384 0 : logic ic_debug_wr_en; // Icache debug wr
385 0 : logic ic_debug_tag_array; // Debug tag array
386 0 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way; // Debug way. Rd or Wr.
387 :
388 0 : logic [25:0] ictag_debug_rd_data; // Debug icache tag.
389 553683 : logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
390 2113749 : logic [63:0] ic_rd_data;
391 231247 : logic [70:0] ic_debug_rd_data; // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
392 0 : logic [70:0] ic_debug_wr_data; // Debug wr cache.
393 :
394 0 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr; // ecc error per bank
395 0 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr; // parity error per bank
396 :
397 1715691 : logic [63:0] ic_premux_data;
398 5537949 : logic ic_sel_premux_data;
399 :
400 : // ICCM ports
401 160019 : logic [pt.ICCM_BITS-1:1] iccm_rw_addr;
402 74 : logic iccm_wren;
403 133416 : logic iccm_rden;
404 0 : logic [2:0] iccm_wr_size;
405 14 : logic [77:0] iccm_wr_data;
406 8 : logic iccm_buf_correct_ecc;
407 8 : logic iccm_correction_state;
408 :
409 136542 : logic [63:0] iccm_rd_data;
410 161274 : logic [77:0] iccm_rd_data_ecc;
411 :
412 316 : logic core_rst_l; // Core reset including rst_l and dbg_rst_l
413 :
414 0 : logic dccm_clk_override;
415 0 : logic icm_clk_override;
416 8 : logic dec_tlu_core_ecc_disable;
417 :
418 :
419 : // zero out the signals not presented at the wrapper instantiation level
420 : `ifdef RV_BUILD_AXI4
421 :
422 : //// AHB LITE BUS
423 0 : logic [31:0] haddr;
424 0 : logic [2:0] hburst;
425 0 : logic hmastlock;
426 0 : logic [3:0] hprot;
427 0 : logic [2:0] hsize;
428 0 : logic [1:0] htrans;
429 0 : logic hwrite;
430 :
431 0 : logic [63:0] hrdata;
432 0 : logic hready;
433 0 : logic hresp;
434 :
435 : // LSU AHB Master
436 0 : logic [31:0] lsu_haddr;
437 0 : logic [2:0] lsu_hburst;
438 0 : logic lsu_hmastlock;
439 0 : logic [3:0] lsu_hprot;
440 0 : logic [2:0] lsu_hsize;
441 0 : logic [1:0] lsu_htrans;
442 0 : logic lsu_hwrite;
443 0 : logic [63:0] lsu_hwdata;
444 :
445 0 : logic [63:0] lsu_hrdata;
446 0 : logic lsu_hready;
447 0 : logic lsu_hresp;
448 : // Debug Syster Bus AHB
449 0 : logic [31:0] sb_haddr;
450 0 : logic [2:0] sb_hburst;
451 0 : logic sb_hmastlock;
452 0 : logic [3:0] sb_hprot;
453 0 : logic [2:0] sb_hsize;
454 0 : logic [1:0] sb_htrans;
455 0 : logic sb_hwrite;
456 0 : logic [63:0] sb_hwdata;
457 :
458 0 : logic [63:0] sb_hrdata;
459 0 : logic sb_hready;
460 0 : logic sb_hresp;
461 :
462 : // DMA Slave
463 0 : logic dma_hsel;
464 0 : logic [31:0] dma_haddr;
465 0 : logic [2:0] dma_hburst;
466 0 : logic dma_hmastlock;
467 0 : logic [3:0] dma_hprot;
468 0 : logic [2:0] dma_hsize;
469 0 : logic [1:0] dma_htrans;
470 0 : logic dma_hwrite;
471 0 : logic [63:0] dma_hwdata;
472 0 : logic dma_hreadyin;
473 :
474 0 : logic [63:0] dma_hrdata;
475 0 : logic dma_hreadyout;
476 0 : logic dma_hresp;
477 :
478 :
479 :
480 : // AHB
481 : assign hrdata[63:0] = '0;
482 : assign hready = '0;
483 : assign hresp = '0;
484 : // LSU
485 : assign lsu_hrdata[63:0] = '0;
486 : assign lsu_hready = '0;
487 : assign lsu_hresp = '0;
488 : // Debu
489 : assign sb_hrdata[63:0] = '0;
490 : assign sb_hready = '0;
491 : assign sb_hresp = '0;
492 :
493 : // DMA
494 : assign dma_hsel = '0;
495 : assign dma_haddr[31:0] = '0;
496 : assign dma_hburst[2:0] = '0;
497 : assign dma_hmastlock = '0;
498 : assign dma_hprot[3:0] = '0;
499 : assign dma_hsize[2:0] = '0;
500 : assign dma_htrans[1:0] = '0;
501 : assign dma_hwrite = '0;
502 : assign dma_hwdata[63:0] = '0;
503 : assign dma_hreadyin = '0;
504 :
505 : `endif // `ifdef RV_BUILD_AXI4
506 :
507 :
508 : `ifdef RV_BUILD_AHB_LITE
509 198108 : wire lsu_axi_awvalid;
510 0 : wire lsu_axi_awready;
511 0 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;
512 9 : wire [31:0] lsu_axi_awaddr;
513 17 : wire [3:0] lsu_axi_awregion;
514 0 : wire [7:0] lsu_axi_awlen;
515 0 : wire [2:0] lsu_axi_awsize;
516 0 : wire [1:0] lsu_axi_awburst;
517 0 : wire lsu_axi_awlock;
518 1254 : wire [3:0] lsu_axi_awcache;
519 0 : wire [2:0] lsu_axi_awprot;
520 0 : wire [3:0] lsu_axi_awqos;
521 :
522 :
523 198108 : wire lsu_axi_wvalid;
524 0 : wire lsu_axi_wready;
525 1606 : wire [63:0] lsu_axi_wdata;
526 38614 : wire [7:0] lsu_axi_wstrb;
527 18 : wire lsu_axi_wlast;
528 :
529 0 : wire lsu_axi_bvalid;
530 18 : wire lsu_axi_bready;
531 0 : wire [1:0] lsu_axi_bresp;
532 0 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;
533 :
534 : // AXI Read Channels
535 232996 : wire lsu_axi_arvalid;
536 0 : wire lsu_axi_arready;
537 0 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;
538 9 : wire [31:0] lsu_axi_araddr;
539 17 : wire [3:0] lsu_axi_arregion;
540 0 : wire [7:0] lsu_axi_arlen;
541 0 : wire [2:0] lsu_axi_arsize;
542 0 : wire [1:0] lsu_axi_arburst;
543 0 : wire lsu_axi_arlock;
544 1254 : wire [3:0] lsu_axi_arcache;
545 0 : wire [2:0] lsu_axi_arprot;
546 0 : wire [3:0] lsu_axi_arqos;
547 :
548 0 : wire lsu_axi_rvalid;
549 18 : wire lsu_axi_rready;
550 0 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;
551 0 : wire [63:0] lsu_axi_rdata;
552 0 : wire [1:0] lsu_axi_rresp;
553 0 : wire lsu_axi_rlast;
554 :
555 : assign lsu_axi_awready = '0;
556 : assign lsu_axi_wready = '0;
557 : assign lsu_axi_bvalid = '0;
558 : assign lsu_axi_bresp = '0;
559 : assign lsu_axi_bid = {pt.LSU_BUS_TAG{1'b0}};
560 : assign lsu_axi_arready = '0;
561 : assign lsu_axi_rvalid = '0;
562 : assign lsu_axi_rid = {pt.LSU_BUS_TAG{1'b0}};
563 : assign lsu_axi_rdata = '0;
564 : assign lsu_axi_rresp = '0;
565 : assign lsu_axi_rlast = '0;
566 : //-------------------------- IFU AXI signals--------------------------
567 : // AXI Write Channels
568 0 : wire ifu_axi_awvalid;
569 18 : wire ifu_axi_awready;
570 0 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;
571 0 : wire [31:0] ifu_axi_awaddr;
572 0 : wire [3:0] ifu_axi_awregion;
573 0 : wire [7:0] ifu_axi_awlen;
574 0 : wire [2:0] ifu_axi_awsize;
575 0 : wire [1:0] ifu_axi_awburst;
576 0 : wire ifu_axi_awlock;
577 0 : wire [3:0] ifu_axi_awcache;
578 0 : wire [2:0] ifu_axi_awprot;
579 0 : wire [3:0] ifu_axi_awqos;
580 :
581 0 : wire ifu_axi_wvalid;
582 18 : wire ifu_axi_wready;
583 0 : wire [63:0] ifu_axi_wdata;
584 0 : wire [7:0] ifu_axi_wstrb;
585 0 : wire ifu_axi_wlast;
586 :
587 0 : wire ifu_axi_bvalid;
588 0 : wire ifu_axi_bready;
589 0 : wire [1:0] ifu_axi_bresp;
590 0 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_bid;
591 :
592 : // AXI Read Channels
593 1413789 : wire ifu_axi_arvalid;
594 0 : wire ifu_axi_arready;
595 829350 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_arid;
596 507900 : wire [31:0] ifu_axi_araddr;
597 20 : wire [3:0] ifu_axi_arregion;
598 0 : wire [7:0] ifu_axi_arlen;
599 0 : wire [2:0] ifu_axi_arsize;
600 0 : wire [1:0] ifu_axi_arburst;
601 0 : wire ifu_axi_arlock;
602 18 : wire [3:0] ifu_axi_arcache;
603 18 : wire [2:0] ifu_axi_arprot;
604 0 : wire [3:0] ifu_axi_arqos;
605 :
606 0 : wire ifu_axi_rvalid;
607 18 : wire ifu_axi_rready;
608 0 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_rid;
609 0 : wire [63:0] ifu_axi_rdata;
610 0 : wire [1:0] ifu_axi_rresp;
611 0 : wire ifu_axi_rlast;
612 :
613 : assign ifu_axi_bvalid = '0;
614 : assign ifu_axi_bresp = '0;
615 : assign ifu_axi_bid = {pt.IFU_BUS_TAG{1'b0}};
616 : assign ifu_axi_arready = '0;
617 : assign ifu_axi_rvalid = '0;
618 : assign ifu_axi_rid = {pt.IFU_BUS_TAG{1'b0}};
619 : assign ifu_axi_rdata = 0;
620 : assign ifu_axi_rresp = '0;
621 : assign ifu_axi_rlast = '0;
622 : //-------------------------- SB AXI signals--------------------------
623 : // AXI Write Channels
624 10 : wire sb_axi_awvalid;
625 0 : wire sb_axi_awready;
626 0 : wire [pt.SB_BUS_TAG-1:0] sb_axi_awid;
627 2 : wire [31:0] sb_axi_awaddr;
628 2 : wire [3:0] sb_axi_awregion;
629 0 : wire [7:0] sb_axi_awlen;
630 0 : wire [2:0] sb_axi_awsize;
631 0 : wire [1:0] sb_axi_awburst;
632 0 : wire sb_axi_awlock;
633 18 : wire [3:0] sb_axi_awcache;
634 0 : wire [2:0] sb_axi_awprot;
635 0 : wire [3:0] sb_axi_awqos;
636 :
637 10 : wire sb_axi_wvalid;
638 0 : wire sb_axi_wready;
639 3 : wire [63:0] sb_axi_wdata;
640 12 : wire [7:0] sb_axi_wstrb;
641 18 : wire sb_axi_wlast;
642 :
643 0 : wire sb_axi_bvalid;
644 18 : wire sb_axi_bready;
645 0 : wire [1:0] sb_axi_bresp;
646 0 : wire [pt.SB_BUS_TAG-1:0] sb_axi_bid;
647 :
648 : // AXI Read Channels
649 8 : wire sb_axi_arvalid;
650 0 : wire sb_axi_arready;
651 0 : wire [pt.SB_BUS_TAG-1:0] sb_axi_arid;
652 2 : wire [31:0] sb_axi_araddr;
653 2 : wire [3:0] sb_axi_arregion;
654 0 : wire [7:0] sb_axi_arlen;
655 0 : wire [2:0] sb_axi_arsize;
656 0 : wire [1:0] sb_axi_arburst;
657 0 : wire sb_axi_arlock;
658 0 : wire [3:0] sb_axi_arcache;
659 0 : wire [2:0] sb_axi_arprot;
660 0 : wire [3:0] sb_axi_arqos;
661 :
662 0 : wire sb_axi_rvalid;
663 18 : wire sb_axi_rready;
664 0 : wire [pt.SB_BUS_TAG-1:0] sb_axi_rid;
665 0 : wire [63:0] sb_axi_rdata;
666 0 : wire [1:0] sb_axi_rresp;
667 0 : wire sb_axi_rlast;
668 :
669 : assign sb_axi_awready = '0;
670 : assign sb_axi_wready = '0;
671 : assign sb_axi_bvalid = '0;
672 : assign sb_axi_bresp = '0;
673 : assign sb_axi_bid = {pt.SB_BUS_TAG{1'b0}};
674 : assign sb_axi_arready = '0;
675 : assign sb_axi_rvalid = '0;
676 : assign sb_axi_rid = {pt.SB_BUS_TAG{1'b0}};
677 : assign sb_axi_rdata = '0;
678 : assign sb_axi_rresp = '0;
679 : assign sb_axi_rlast = '0;
680 : //-------------------------- DMA AXI signals--------------------------
681 : // AXI Write Channels
682 0 : wire dma_axi_awvalid;
683 18 : wire dma_axi_awready;
684 0 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_awid;
685 0 : wire [31:0] dma_axi_awaddr;
686 0 : wire [2:0] dma_axi_awsize;
687 0 : wire [2:0] dma_axi_awprot;
688 0 : wire [7:0] dma_axi_awlen;
689 0 : wire [1:0] dma_axi_awburst;
690 :
691 :
692 0 : wire dma_axi_wvalid;
693 18 : wire dma_axi_wready;
694 0 : wire [63:0] dma_axi_wdata;
695 0 : wire [7:0] dma_axi_wstrb;
696 0 : wire dma_axi_wlast;
697 :
698 : assign dma_axi_awvalid = 1'b0;
699 : assign dma_axi_awid = {pt.DMA_BUS_TAG{1'b0}};
700 : assign dma_axi_awaddr = 32'd0;
701 : assign dma_axi_awsize = 3'd0;
702 : assign dma_axi_awprot = 3'd0;
703 : assign dma_axi_awlen = 8'd0;
704 : assign dma_axi_awburst = 2'd0;
705 :
706 :
707 : assign dma_axi_wvalid = 1'b0;
708 : assign dma_axi_wdata = 64'd0;
709 : assign dma_axi_wstrb = 8'd0;
710 : assign dma_axi_wlast = 1'b0;
711 :
712 :
713 0 : wire dma_axi_bvalid;
714 0 : wire dma_axi_bready;
715 0 : wire [1:0] dma_axi_bresp;
716 0 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_bid;
717 :
718 : assign dma_axi_bready = 1'b0;
719 : // AXI Read Channels
720 0 : wire dma_axi_arvalid;
721 18 : wire dma_axi_arready;
722 0 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_arid;
723 0 : wire [31:0] dma_axi_araddr;
724 0 : wire [2:0] dma_axi_arsize;
725 0 : wire [2:0] dma_axi_arprot;
726 0 : wire [7:0] dma_axi_arlen;
727 0 : wire [1:0] dma_axi_arburst;
728 :
729 : assign dma_axi_arvalid = 1'b0;
730 : assign dma_axi_arid = {pt.DMA_BUS_TAG{1'b0}};
731 : assign dma_axi_araddr = 32'd0;
732 : assign dma_axi_arsize = 3'd0;
733 : assign dma_axi_arprot = 3'd0;
734 : assign dma_axi_arlen = 8'd0;
735 : assign dma_axi_arburst = 2'd0;
736 :
737 :
738 :
739 0 : wire dma_axi_rvalid;
740 0 : wire dma_axi_rready;
741 0 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_rid;
742 0 : wire [63:0] dma_axi_rdata;
743 0 : wire [1:0] dma_axi_rresp;
744 18 : wire dma_axi_rlast;
745 :
746 : assign dma_axi_rready = 1'b0;
747 : // AXI
748 : assign ifu_axi_awready = 1'b1;
749 : assign ifu_axi_wready = 1'b1;
750 : assign ifu_axi_bvalid = '0;
751 : assign ifu_axi_bresp[1:0] = '0;
752 : assign ifu_axi_bid[pt.IFU_BUS_TAG-1:0] = '0;
753 :
754 : `endif // `ifdef RV_BUILD_AHB_LITE
755 :
756 : // DMI (core)
757 240 : logic dmi_en;
758 0 : logic [6:0] dmi_addr;
759 112 : logic dmi_wr_en;
760 20 : logic [31:0] dmi_wdata;
761 12 : logic [31:0] dmi_rdata;
762 :
763 : // DMI (core)
764 240 : logic dmi_reg_en;
765 0 : logic [6:0] dmi_reg_addr;
766 112 : logic dmi_reg_wr_en;
767 20 : logic [31:0] dmi_reg_wdata;
768 12 : logic [31:0] dmi_reg_rdata;
769 :
770 : // Instantiate the el2_veer core
771 : el2_veer #(.pt(pt)) veer (
772 : .clk(clk),
773 : .*
774 : );
775 :
776 : // Instantiate the mem
777 : el2_mem #(.pt(pt)) mem (
778 : .clk(active_l2clk),
779 : .rst_l(core_rst_l),
780 : .mem_export(el2_mem_export),
781 : .*
782 : );
783 :
784 :
785 : // JTAG/DMI instance
786 : dmi_wrapper dmi_wrapper (
787 : // JTAG signals
788 : .trst_n (jtag_trst_n), // JTAG reset
789 : .tck (jtag_tck), // JTAG clock
790 : .tms (jtag_tms), // Test mode select
791 : .tdi (jtag_tdi), // Test Data Input
792 : .tdo (jtag_tdo), // Test Data Output
793 : .tdoEnable (jtag_tdoEn), // Test Data Output enable
794 : // Processor Signals
795 : .core_rst_n (dbg_rst_l), // Debug reset, active low
796 : .core_clk (clk), // Core clock
797 : .jtag_id (jtag_id), // JTAG ID
798 : .rd_data (dmi_rdata), // Read data from Processor
799 : .reg_wr_data (dmi_wdata), // Write data to Processor
800 : .reg_wr_addr (dmi_addr), // Write address to Processor
801 : .reg_en (dmi_en), // Write interface bit to Processor
802 : .reg_wr_en (dmi_wr_en), // Write enable to Processor
803 : .dmi_hard_reset ()
804 : );
805 :
806 : // DMI core/uncore mux
807 : dmi_mux dmi_mux (
808 : .uncore_enable (dmi_uncore_enable),
809 :
810 : .dmi_en (dmi_en),
811 : .dmi_wr_en (dmi_wr_en),
812 : .dmi_addr (dmi_addr),
813 : .dmi_wdata (dmi_wdata),
814 : .dmi_rdata (dmi_rdata),
815 :
816 : .dmi_core_en (dmi_reg_en),
817 : .dmi_core_wr_en (dmi_reg_wr_en),
818 : .dmi_core_addr (dmi_reg_addr),
819 : .dmi_core_wdata (dmi_reg_wdata),
820 : .dmi_core_rdata (dmi_reg_rdata),
821 :
822 : .dmi_uncore_en (dmi_uncore_en),
823 : .dmi_uncore_wr_en (dmi_uncore_wr_en),
824 : .dmi_uncore_addr (dmi_uncore_addr),
825 : .dmi_uncore_wdata (dmi_uncore_wdata),
826 : .dmi_uncore_rdata (dmi_uncore_rdata)
827 : );
828 :
829 : `ifdef RV_ASSERT_ON
830 : // to avoid internal assertions failure at time 0
831 : initial begin
832 : $assertoff(0, veer);
833 : @(negedge clk) $asserton(0, veer);
834 : end
835 : `endif
836 :
837 : endmodule
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