Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 : //********************************************************************************
17 : // $Id$
18 : //
19 : // Function: Top level VeeR core file
20 : // Comments:
21 : //
22 : //********************************************************************************
23 : module el2_veer
24 : import el2_pkg::*;
25 : #(
26 : `include "el2_param.vh"
27 : )
28 : (
29 61045677 : input logic clk,
30 316 : input logic rst_l,
31 316 : input logic dbg_rst_l,
32 0 : input logic [31:1] rst_vec,
33 16 : input logic nmi_int,
34 0 : input logic [31:1] nmi_vec,
35 316 : output logic core_rst_l, // This is "rst_l | dbg_rst_l"
36 :
37 61045677 : output logic active_l2clk,
38 61045677 : output logic free_l2clk,
39 :
40 572576 : output logic [31:0] trace_rv_i_insn_ip,
41 308 : output logic [31:0] trace_rv_i_address_ip,
42 6090692 : output logic trace_rv_i_valid_ip,
43 5114 : output logic trace_rv_i_exception_ip,
44 0 : output logic [4:0] trace_rv_i_ecause_ip,
45 22 : output logic trace_rv_i_interrupt_ip,
46 52 : output logic [31:0] trace_rv_i_tval_ip,
47 :
48 :
49 0 : output logic dccm_clk_override,
50 0 : output logic icm_clk_override,
51 8 : output logic dec_tlu_core_ecc_disable,
52 :
53 : // external halt/run interface
54 0 : input logic i_cpu_halt_req, // Asynchronous Halt request to CPU
55 0 : input logic i_cpu_run_req, // Asynchronous Restart request to CPU
56 0 : output logic o_cpu_halt_ack, // Core Acknowledge to Halt request
57 0 : output logic o_cpu_halt_status, // 1'b1 indicates processor is halted
58 0 : output logic o_cpu_run_ack, // Core Acknowledge to run request
59 0 : output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
60 :
61 0 : input logic [31:4] core_id, // CORE ID
62 :
63 : // external MPC halt/run interface
64 0 : input logic mpc_debug_halt_req, // Async halt request
65 316 : input logic mpc_debug_run_req, // Async run request
66 316 : input logic mpc_reset_run_req, // Run/halt after reset
67 0 : output logic mpc_debug_halt_ack, // Halt ack
68 316 : output logic mpc_debug_run_ack, // Run ack
69 0 : output logic debug_brkpt_status, // debug breakpoint
70 :
71 340148 : output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
72 514626 : output logic dec_tlu_perfcnt1,
73 312914 : output logic dec_tlu_perfcnt2,
74 48468 : output logic dec_tlu_perfcnt3,
75 :
76 : // DCCM ports
77 262892 : output logic dccm_wren,
78 561000 : output logic dccm_rden,
79 18811 : output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
80 18811 : output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
81 470114 : output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
82 676449 : output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
83 5374 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
84 5374 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
85 :
86 47172 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
87 47172 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
88 :
89 : // ICCM ports
90 160019 : output logic [pt.ICCM_BITS-1:1] iccm_rw_addr,
91 74 : output logic iccm_wren,
92 133416 : output logic iccm_rden,
93 0 : output logic [2:0] iccm_wr_size,
94 14 : output logic [77:0] iccm_wr_data,
95 8 : output logic iccm_buf_correct_ecc,
96 8 : output logic iccm_correction_state,
97 :
98 136542 : input logic [63:0] iccm_rd_data,
99 161274 : input logic [77:0] iccm_rd_data_ecc,
100 :
101 : // ICache , ITAG ports
102 326 : output logic [31:1] ic_rw_addr,
103 255918 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,
104 10432 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,
105 680092 : output logic ic_rd_en,
106 :
107 553683 : output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
108 2113749 : input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
109 231247 : input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
110 0 : input logic [25:0] ictag_debug_rd_data,// Debug icache tag.
111 0 : output logic [70:0] ic_debug_wr_data, // Debug wr cache.
112 :
113 0 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
114 0 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
115 1715691 : output logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
116 5537949 : output logic ic_sel_premux_data, // Select premux data
117 :
118 :
119 0 : output logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
120 0 : output logic ic_debug_rd_en, // Icache debug rd
121 0 : output logic ic_debug_wr_en, // Icache debug wr
122 0 : output logic ic_debug_tag_array, // Debug tag array
123 0 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
124 :
125 :
126 :
127 109586 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
128 0 : input logic ic_tag_perr, // Icache Tag parity error
129 :
130 : //-------------------------- LSU AXI signals--------------------------
131 : // AXI Write Channels
132 848785 : output logic lsu_axi_awvalid,
133 660317 : input logic lsu_axi_awready,
134 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
135 400 : output logic [31:0] lsu_axi_awaddr,
136 314 : output logic [3:0] lsu_axi_awregion,
137 0 : output logic [7:0] lsu_axi_awlen,
138 0 : output logic [2:0] lsu_axi_awsize,
139 0 : output logic [1:0] lsu_axi_awburst,
140 0 : output logic lsu_axi_awlock,
141 2985 : output logic [3:0] lsu_axi_awcache,
142 0 : output logic [2:0] lsu_axi_awprot,
143 0 : output logic [3:0] lsu_axi_awqos,
144 :
145 848785 : output logic lsu_axi_wvalid,
146 660317 : input logic lsu_axi_wready,
147 31369 : output logic [63:0] lsu_axi_wdata,
148 224176 : output logic [7:0] lsu_axi_wstrb,
149 317 : output logic lsu_axi_wlast,
150 :
151 660078 : input logic lsu_axi_bvalid,
152 317 : output logic lsu_axi_bready,
153 0 : input logic [1:0] lsu_axi_bresp,
154 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
155 :
156 : // AXI Read Channels
157 863054 : output logic lsu_axi_arvalid,
158 672407 : input logic lsu_axi_arready,
159 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
160 400 : output logic [31:0] lsu_axi_araddr,
161 314 : output logic [3:0] lsu_axi_arregion,
162 0 : output logic [7:0] lsu_axi_arlen,
163 0 : output logic [2:0] lsu_axi_arsize,
164 0 : output logic [1:0] lsu_axi_arburst,
165 0 : output logic lsu_axi_arlock,
166 2985 : output logic [3:0] lsu_axi_arcache,
167 0 : output logic [2:0] lsu_axi_arprot,
168 0 : output logic [3:0] lsu_axi_arqos,
169 :
170 672110 : input logic lsu_axi_rvalid,
171 317 : output logic lsu_axi_rready,
172 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
173 26474 : input logic [63:0] lsu_axi_rdata,
174 0 : input logic [1:0] lsu_axi_rresp,
175 672118 : input logic lsu_axi_rlast,
176 :
177 : //-------------------------- IFU AXI signals--------------------------
178 : // AXI Write Channels
179 0 : output logic ifu_axi_awvalid,
180 18 : input logic ifu_axi_awready,
181 0 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
182 0 : output logic [31:0] ifu_axi_awaddr,
183 0 : output logic [3:0] ifu_axi_awregion,
184 0 : output logic [7:0] ifu_axi_awlen,
185 0 : output logic [2:0] ifu_axi_awsize,
186 0 : output logic [1:0] ifu_axi_awburst,
187 0 : output logic ifu_axi_awlock,
188 0 : output logic [3:0] ifu_axi_awcache,
189 0 : output logic [2:0] ifu_axi_awprot,
190 0 : output logic [3:0] ifu_axi_awqos,
191 :
192 0 : output logic ifu_axi_wvalid,
193 18 : input logic ifu_axi_wready,
194 0 : output logic [63:0] ifu_axi_wdata,
195 0 : output logic [7:0] ifu_axi_wstrb,
196 0 : output logic ifu_axi_wlast,
197 :
198 0 : input logic ifu_axi_bvalid,
199 0 : output logic ifu_axi_bready,
200 0 : input logic [1:0] ifu_axi_bresp,
201 0 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
202 :
203 : // AXI Read Channels
204 5820149 : output logic ifu_axi_arvalid,
205 8831737 : input logic ifu_axi_arready,
206 3541092 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
207 2426230 : output logic [31:0] ifu_axi_araddr,
208 320 : output logic [3:0] ifu_axi_arregion,
209 0 : output logic [7:0] ifu_axi_arlen,
210 0 : output logic [2:0] ifu_axi_arsize,
211 0 : output logic [1:0] ifu_axi_arburst,
212 0 : output logic ifu_axi_arlock,
213 317 : output logic [3:0] ifu_axi_arcache,
214 317 : output logic [2:0] ifu_axi_arprot,
215 0 : output logic [3:0] ifu_axi_arqos,
216 :
217 8831439 : input logic ifu_axi_rvalid,
218 317 : output logic ifu_axi_rready,
219 888509 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
220 734885 : input logic [63:0] ifu_axi_rdata,
221 0 : input logic [1:0] ifu_axi_rresp,
222 8831439 : input logic ifu_axi_rlast,
223 :
224 : //-------------------------- SB AXI signals--------------------------
225 : // AXI Write Channels
226 20 : output logic sb_axi_awvalid,
227 10 : input logic sb_axi_awready,
228 0 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
229 4 : output logic [31:0] sb_axi_awaddr,
230 4 : output logic [3:0] sb_axi_awregion,
231 0 : output logic [7:0] sb_axi_awlen,
232 0 : output logic [2:0] sb_axi_awsize,
233 0 : output logic [1:0] sb_axi_awburst,
234 0 : output logic sb_axi_awlock,
235 317 : output logic [3:0] sb_axi_awcache,
236 0 : output logic [2:0] sb_axi_awprot,
237 0 : output logic [3:0] sb_axi_awqos,
238 :
239 20 : output logic sb_axi_wvalid,
240 10 : input logic sb_axi_wready,
241 6 : output logic [63:0] sb_axi_wdata,
242 24 : output logic [7:0] sb_axi_wstrb,
243 317 : output logic sb_axi_wlast,
244 :
245 10 : input logic sb_axi_bvalid,
246 317 : output logic sb_axi_bready,
247 0 : input logic [1:0] sb_axi_bresp,
248 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
249 :
250 : // AXI Read Channels
251 16 : output logic sb_axi_arvalid,
252 8 : input logic sb_axi_arready,
253 0 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
254 4 : output logic [31:0] sb_axi_araddr,
255 4 : output logic [3:0] sb_axi_arregion,
256 0 : output logic [7:0] sb_axi_arlen,
257 0 : output logic [2:0] sb_axi_arsize,
258 0 : output logic [1:0] sb_axi_arburst,
259 0 : output logic sb_axi_arlock,
260 0 : output logic [3:0] sb_axi_arcache,
261 0 : output logic [2:0] sb_axi_arprot,
262 0 : output logic [3:0] sb_axi_arqos,
263 :
264 8 : input logic sb_axi_rvalid,
265 317 : output logic sb_axi_rready,
266 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
267 1 : input logic [63:0] sb_axi_rdata,
268 0 : input logic [1:0] sb_axi_rresp,
269 8 : input logic sb_axi_rlast,
270 :
271 : //-------------------------- DMA AXI signals--------------------------
272 : // AXI Write Channels
273 66 : input logic dma_axi_awvalid,
274 317 : output logic dma_axi_awready,
275 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
276 391 : input logic [31:0] dma_axi_awaddr,
277 0 : input logic [2:0] dma_axi_awsize,
278 0 : input logic [2:0] dma_axi_awprot,
279 0 : input logic [7:0] dma_axi_awlen,
280 0 : input logic [1:0] dma_axi_awburst,
281 :
282 :
283 66 : input logic dma_axi_wvalid,
284 317 : output logic dma_axi_wready,
285 29763 : input logic [63:0] dma_axi_wdata,
286 185562 : input logic [7:0] dma_axi_wstrb,
287 298 : input logic dma_axi_wlast,
288 :
289 66 : output logic dma_axi_bvalid,
290 66 : input logic dma_axi_bready,
291 0 : output logic [1:0] dma_axi_bresp,
292 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
293 :
294 : // AXI Read Channels
295 0 : input logic dma_axi_arvalid,
296 317 : output logic dma_axi_arready,
297 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
298 391 : input logic [31:0] dma_axi_araddr,
299 0 : input logic [2:0] dma_axi_arsize,
300 0 : input logic [2:0] dma_axi_arprot,
301 0 : input logic [7:0] dma_axi_arlen,
302 0 : input logic [1:0] dma_axi_arburst,
303 :
304 0 : output logic dma_axi_rvalid,
305 0 : input logic dma_axi_rready,
306 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
307 12 : output logic [63:0] dma_axi_rdata,
308 0 : output logic [1:0] dma_axi_rresp,
309 317 : output logic dma_axi_rlast,
310 :
311 :
312 : //// AHB LITE BUS
313 15 : output logic [31:0] haddr,
314 0 : output logic [2:0] hburst,
315 0 : output logic hmastlock,
316 0 : output logic [3:0] hprot,
317 0 : output logic [2:0] hsize,
318 1413789 : output logic [1:0] htrans,
319 0 : output logic hwrite,
320 :
321 238151 : input logic [63:0] hrdata,
322 18 : input logic hready,
323 0 : input logic hresp,
324 :
325 : // LSU AHB Master
326 9 : output logic [31:0] lsu_haddr,
327 0 : output logic [2:0] lsu_hburst,
328 0 : output logic lsu_hmastlock,
329 0 : output logic [3:0] lsu_hprot,
330 0 : output logic [2:0] lsu_hsize,
331 434682 : output logic [1:0] lsu_htrans,
332 85537 : output logic lsu_hwrite,
333 5246 : output logic [63:0] lsu_hwdata,
334 :
335 2286 : input logic [63:0] lsu_hrdata,
336 18 : input logic lsu_hready,
337 0 : input logic lsu_hresp,
338 :
339 : //System Bus Debug Master
340 2 : output logic [31:0] sb_haddr,
341 0 : output logic [2:0] sb_hburst,
342 0 : output logic sb_hmastlock,
343 0 : output logic [3:0] sb_hprot,
344 0 : output logic [2:0] sb_hsize,
345 18 : output logic [1:0] sb_htrans,
346 7 : output logic sb_hwrite,
347 3 : output logic [63:0] sb_hwdata,
348 :
349 4 : input logic [63:0] sb_hrdata,
350 1 : input logic sb_hready,
351 0 : input logic sb_hresp,
352 :
353 : // DMA Slave
354 18 : input logic dma_hsel,
355 0 : input logic [31:0] dma_haddr,
356 0 : input logic [2:0] dma_hburst,
357 0 : input logic dma_hmastlock,
358 0 : input logic [3:0] dma_hprot,
359 0 : input logic [2:0] dma_hsize,
360 0 : input logic [1:0] dma_htrans,
361 0 : input logic dma_hwrite,
362 0 : input logic [63:0] dma_hwdata,
363 18 : input logic dma_hreadyin,
364 :
365 0 : output logic [63:0] dma_hrdata,
366 18 : output logic dma_hreadyout,
367 0 : output logic dma_hresp,
368 :
369 316 : input logic lsu_bus_clk_en,
370 316 : input logic ifu_bus_clk_en,
371 316 : input logic dbg_bus_clk_en,
372 316 : input logic dma_bus_clk_en,
373 :
374 240 : input logic dmi_reg_en, // read or write
375 0 : input logic [6:0] dmi_reg_addr, // address of DM register
376 112 : input logic dmi_reg_wr_en, // write instruction
377 20 : input logic [31:0] dmi_reg_wdata, // write data
378 12 : output logic [31:0] dmi_reg_rdata,
379 :
380 : // ICCM/DCCM ECC status
381 8 : output logic iccm_ecc_single_error,
382 4 : output logic iccm_ecc_double_error,
383 4 : output logic dccm_ecc_single_error,
384 4 : output logic dccm_ecc_double_error,
385 :
386 0 : input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
387 12 : input logic timer_int,
388 14 : input logic soft_int,
389 0 : input logic scan_mode
390 : );
391 :
392 :
393 :
394 :
395 189884 : logic [63:0] hwdata_nc;
396 : //----------------------------------------------------------------------
397 : //
398 : //----------------------------------------------------------------------
399 :
400 6117789 : logic ifu_pmu_instr_aligned;
401 0 : logic ifu_ic_error_start;
402 0 : logic ifu_iccm_dma_rd_ecc_single_err;
403 8 : logic ifu_iccm_rd_ecc_single_err;
404 4 : logic ifu_iccm_rd_ecc_double_err;
405 4 : logic lsu_dccm_rd_ecc_single_err;
406 4 : logic lsu_dccm_rd_ecc_double_err;
407 :
408 435561 : logic lsu_axi_awready_ahb;
409 435561 : logic lsu_axi_wready_ahb;
410 201996 : logic lsu_axi_bvalid_ahb;
411 0 : logic lsu_axi_bready_ahb;
412 0 : logic [1:0] lsu_axi_bresp_ahb;
413 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_ahb;
414 431475 : logic lsu_axi_arready_ahb;
415 251552 : logic lsu_axi_rvalid_ahb;
416 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_ahb;
417 2286 : logic [63:0] lsu_axi_rdata_ahb;
418 0 : logic [1:0] lsu_axi_rresp_ahb;
419 18 : logic lsu_axi_rlast_ahb;
420 :
421 1095878 : logic lsu_axi_awready_int;
422 1095878 : logic lsu_axi_wready_int;
423 862074 : logic lsu_axi_bvalid_int;
424 299 : logic lsu_axi_bready_int;
425 0 : logic [1:0] lsu_axi_bresp_int;
426 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_int;
427 1103882 : logic lsu_axi_arready_int;
428 923662 : logic lsu_axi_rvalid_int;
429 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_int;
430 28760 : logic [63:0] lsu_axi_rdata_int;
431 0 : logic [1:0] lsu_axi_rresp_int;
432 672136 : logic lsu_axi_rlast_int;
433 :
434 1413801 : logic ifu_axi_awready_ahb;
435 1413801 : logic ifu_axi_wready_ahb;
436 0 : logic ifu_axi_bvalid_ahb;
437 0 : logic ifu_axi_bready_ahb;
438 0 : logic [1:0] ifu_axi_bresp_ahb;
439 277770 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_ahb;
440 1413801 : logic ifu_axi_arready_ahb;
441 2827569 : logic ifu_axi_rvalid_ahb;
442 277770 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_ahb;
443 238150 : logic [63:0] ifu_axi_rdata_ahb;
444 0 : logic [1:0] ifu_axi_rresp_ahb;
445 18 : logic ifu_axi_rlast_ahb;
446 :
447 1413801 : logic ifu_axi_awready_int;
448 1413801 : logic ifu_axi_wready_int;
449 0 : logic ifu_axi_bvalid_int;
450 0 : logic ifu_axi_bready_int;
451 0 : logic [1:0] ifu_axi_bresp_int;
452 277770 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_int;
453 10245538 : logic ifu_axi_arready_int;
454 11659008 : logic ifu_axi_rvalid_int;
455 1166279 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_int;
456 973035 : logic [63:0] ifu_axi_rdata_int;
457 0 : logic [1:0] ifu_axi_rresp_int;
458 8831457 : logic ifu_axi_rlast_int;
459 :
460 36 : logic sb_axi_awready_ahb;
461 36 : logic sb_axi_wready_ahb;
462 10 : logic sb_axi_bvalid_ahb;
463 0 : logic sb_axi_bready_ahb;
464 0 : logic [1:0] sb_axi_bresp_ahb;
465 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_bid_ahb;
466 36 : logic sb_axi_arready_ahb;
467 8 : logic sb_axi_rvalid_ahb;
468 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_rid_ahb;
469 4 : logic [63:0] sb_axi_rdata_ahb;
470 0 : logic [1:0] sb_axi_rresp_ahb;
471 18 : logic sb_axi_rlast_ahb;
472 :
473 46 : logic sb_axi_awready_int;
474 46 : logic sb_axi_wready_int;
475 20 : logic sb_axi_bvalid_int;
476 299 : logic sb_axi_bready_int;
477 0 : logic [1:0] sb_axi_bresp_int;
478 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_bid_int;
479 44 : logic sb_axi_arready_int;
480 16 : logic sb_axi_rvalid_int;
481 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_rid_int;
482 5 : logic [63:0] sb_axi_rdata_int;
483 0 : logic [1:0] sb_axi_rresp_int;
484 26 : logic sb_axi_rlast_int;
485 :
486 0 : logic dma_axi_awvalid_ahb;
487 0 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_ahb;
488 0 : logic [31:0] dma_axi_awaddr_ahb;
489 0 : logic [2:0] dma_axi_awsize_ahb;
490 0 : logic [2:0] dma_axi_awprot_ahb;
491 0 : logic [7:0] dma_axi_awlen_ahb;
492 0 : logic [1:0] dma_axi_awburst_ahb;
493 0 : logic dma_axi_wvalid_ahb;
494 0 : logic [63:0] dma_axi_wdata_ahb;
495 0 : logic [7:0] dma_axi_wstrb_ahb;
496 18 : logic dma_axi_wlast_ahb;
497 18 : logic dma_axi_bready_ahb;
498 0 : logic dma_axi_arvalid_ahb;
499 0 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_ahb;
500 0 : logic [31:0] dma_axi_araddr_ahb;
501 0 : logic [2:0] dma_axi_arsize_ahb;
502 0 : logic [2:0] dma_axi_arprot_ahb;
503 0 : logic [7:0] dma_axi_arlen_ahb;
504 0 : logic [1:0] dma_axi_arburst_ahb;
505 18 : logic dma_axi_rready_ahb;
506 :
507 66 : logic dma_axi_awvalid_int;
508 0 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_int;
509 391 : logic [31:0] dma_axi_awaddr_int;
510 0 : logic [2:0] dma_axi_awsize_int;
511 0 : logic [2:0] dma_axi_awprot_int;
512 0 : logic [7:0] dma_axi_awlen_int;
513 0 : logic [1:0] dma_axi_awburst_int;
514 66 : logic dma_axi_wvalid_int;
515 29763 : logic [63:0] dma_axi_wdata_int;
516 185562 : logic [7:0] dma_axi_wstrb_int;
517 316 : logic dma_axi_wlast_int;
518 84 : logic dma_axi_bready_int;
519 0 : logic dma_axi_arvalid_int;
520 0 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_int;
521 391 : logic [31:0] dma_axi_araddr_int;
522 0 : logic [2:0] dma_axi_arsize_int;
523 0 : logic [2:0] dma_axi_arprot_int;
524 0 : logic [7:0] dma_axi_arlen_int;
525 0 : logic [1:0] dma_axi_arburst_int;
526 18 : logic dma_axi_rready_int;
527 :
528 :
529 : // Icache debug
530 0 : logic [70:0] ifu_ic_debug_rd_data; // diagnostic icache read data
531 0 : logic ifu_ic_debug_rd_data_valid; // diagnostic icache read data valid
532 0 : el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
533 :
534 :
535 5071983 : logic dec_i0_rs1_en_d;
536 3530031 : logic dec_i0_rs2_en_d;
537 399514 : logic [31:0] gpr_i0_rs1_d;
538 589836 : logic [31:0] gpr_i0_rs2_d;
539 :
540 307463 : logic [31:0] dec_i0_result_r;
541 606727 : logic [31:0] exu_i0_result_x;
542 308 : logic [31:1] exu_i0_pc_x;
543 313 : logic [31:1] exu_npc_r;
544 :
545 1460 : el2_alu_pkt_t i0_ap;
546 :
547 : // Trigger signals
548 0 : el2_trigger_pkt_t [3:0] trigger_pkt_any;
549 0 : logic [3:0] lsu_trigger_match_m;
550 :
551 :
552 2128078 : logic [31:0] dec_i0_immed_d;
553 122206 : logic [12:1] dec_i0_br_immed_d;
554 552640 : logic dec_i0_select_pc_d;
555 :
556 1288 : logic [31:1] dec_i0_pc_d;
557 79890 : logic [3:0] dec_i0_rs1_bypass_en_d;
558 8622 : logic [3:0] dec_i0_rs2_bypass_en_d;
559 :
560 5340072 : logic dec_i0_alu_decode_d;
561 3829266 : logic dec_i0_branch_d;
562 :
563 5819356 : logic ifu_miss_state_idle;
564 0 : logic dec_tlu_flush_noredir_r;
565 0 : logic dec_tlu_flush_leak_one_r;
566 8 : logic dec_tlu_flush_err_r;
567 5935827 : logic ifu_i0_valid;
568 467650 : logic [31:0] ifu_i0_instr;
569 1288 : logic [31:1] ifu_i0_pc;
570 :
571 670967 : logic exu_flush_final;
572 :
573 226500 : logic [31:1] exu_flush_path_final;
574 :
575 411891 : logic [31:0] exu_lsu_rs1_d;
576 81330 : logic [31:0] exu_lsu_rs2_d;
577 :
578 :
579 621347 : el2_lsu_pkt_t lsu_p;
580 5414233 : logic dec_qual_lsu_d;
581 :
582 2264291 : logic dec_lsu_valid_raw_d;
583 269947 : logic [11:0] dec_lsu_offset_d;
584 :
585 38395 : logic [31:0] lsu_result_m;
586 29134 : logic [31:0] lsu_result_corr_r; // This is the ECC corrected data going to RF
587 4 : logic lsu_single_ecc_error_incr; // Increment the ecc counter
588 4 : el2_lsu_error_pkt_t lsu_error_pkt_r;
589 0 : logic lsu_imprecise_error_load_any;
590 0 : logic lsu_imprecise_error_store_any;
591 400 : logic [31:0] lsu_imprecise_error_addr_any;
592 48954 : logic lsu_load_stall_any; // This is for blocking loads
593 59278 : logic lsu_store_stall_any; // This is for blocking stores
594 1337876 : logic lsu_idle_any; // doesn't include DMA
595 1337559 : logic lsu_active; // lsu is active. used for clock
596 :
597 :
598 24694 : logic [31:1] lsu_fir_addr; // fast interrupt address
599 0 : logic [1:0] lsu_fir_error; // Error during fast interrupt lookup
600 :
601 : // Non-blocking loads
602 875736 : logic lsu_nonblock_load_valid_m;
603 502715 : logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m;
604 0 : logic lsu_nonblock_load_inv_r;
605 502712 : logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r;
606 914838 : logic lsu_nonblock_load_data_valid;
607 36596 : logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag;
608 71538 : logic [31:0] lsu_nonblock_load_data;
609 :
610 74908 : logic dec_csr_ren_d;
611 7433 : logic [31:0] dec_csr_rddata_d;
612 :
613 3984 : logic [31:0] exu_csr_rs1_x;
614 :
615 6089967 : logic dec_tlu_i0_commit_cmt;
616 58558 : logic dec_tlu_flush_lower_r;
617 58558 : logic dec_tlu_flush_lower_wb;
618 29644 : logic dec_tlu_i0_kill_writeb_r; // I0 is flushed, don't writeback any results to arch state
619 18866 : logic dec_tlu_fence_i_r; // flush is a fence_i rfnpc, flush icache
620 :
621 24682 : logic [31:1] dec_tlu_flush_path_r;
622 0 : logic [31:0] dec_tlu_mrac_ff; // CSR for memory region control
623 :
624 5697455 : logic ifu_i0_pc4;
625 :
626 0 : el2_mul_pkt_t mul_p;
627 :
628 75168 : el2_div_pkt_t div_p;
629 2758 : logic dec_div_cancel;
630 :
631 23364 : logic [31:0] exu_div_result;
632 151680 : logic exu_div_wren;
633 :
634 6117789 : logic dec_i0_decode_d;
635 :
636 :
637 137876 : logic [31:1] pred_correct_npc_x;
638 :
639 779556 : el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
640 :
641 34374 : el2_predict_pkt_t exu_mp_pkt;
642 298748 : logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr;
643 376371 : logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr;
644 195580 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
645 115632 : logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag;
646 :
647 364495 : logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r;
648 2673518 : logic [1:0] exu_i0_br_hist_r;
649 26458 : logic exu_i0_br_error_r;
650 9602 : logic exu_i0_br_start_error_r;
651 2962168 : logic exu_i0_br_valid_r;
652 408435 : logic exu_i0_br_mp_r;
653 2363578 : logic exu_i0_br_middle_r;
654 :
655 2107869 : logic exu_i0_br_way_r;
656 :
657 187344 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
658 :
659 0 : logic dma_dccm_req;
660 66 : logic dma_iccm_req;
661 12 : logic [2:0] dma_mem_tag;
662 0 : logic [31:0] dma_mem_addr;
663 0 : logic [2:0] dma_mem_sz;
664 18 : logic dma_mem_write;
665 12 : logic [63:0] dma_mem_wdata;
666 :
667 0 : logic dccm_dma_rvalid;
668 4 : logic dccm_dma_ecc_error;
669 12 : logic [2:0] dccm_dma_rtag;
670 39560 : logic [63:0] dccm_dma_rdata;
671 0 : logic iccm_dma_rvalid;
672 4 : logic iccm_dma_ecc_error;
673 12 : logic [2:0] iccm_dma_rtag;
674 0 : logic [63:0] iccm_dma_rdata;
675 :
676 0 : logic dma_dccm_stall_any; // Stall the ld/st in decode if asserted
677 26 : logic dma_iccm_stall_any; // Stall the fetch
678 2213494 : logic dccm_ready;
679 635313 : logic iccm_ready;
680 :
681 0 : logic dma_pmu_dccm_read;
682 0 : logic dma_pmu_dccm_write;
683 0 : logic dma_pmu_any_read;
684 66 : logic dma_pmu_any_write;
685 :
686 196 : logic ifu_i0_icaf;
687 270 : logic [1:0] ifu_i0_icaf_type;
688 :
689 :
690 86 : logic ifu_i0_icaf_second;
691 2 : logic ifu_i0_dbecc;
692 0 : logic iccm_dma_sb_error;
693 :
694 200678 : el2_br_pkt_t i0_brp;
695 649442 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
696 619182 : logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
697 21202 : logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
698 :
699 0 : logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
700 0 : logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index
701 :
702 :
703 504548 : el2_predict_pkt_t dec_i0_predict_p_d;
704 :
705 619182 : logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d; // DEC predict fghr
706 649442 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d; // DEC predict index
707 21202 : logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d; // DEC predict branch tag
708 :
709 : // PIC ports
710 0 : logic picm_wren;
711 0 : logic picm_rden;
712 0 : logic picm_mken;
713 429 : logic [31:0] picm_rdaddr;
714 429 : logic [31:0] picm_wraddr;
715 92602 : logic [31:0] picm_wr_data;
716 0 : logic [31:0] picm_rd_data;
717 :
718 : // feature disable from mfdc
719 0 : logic dec_tlu_external_ldfwd_disable; // disable external load forwarding
720 0 : logic dec_tlu_bpred_disable;
721 4 : logic dec_tlu_wb_coalescing_disable;
722 301 : logic dec_tlu_sideeffect_posted_disable;
723 321 : logic [2:0] dec_tlu_dma_qos_prty; // DMA QoS priority coming from MFDC [18:16]
724 :
725 : // clock gating overrides from mcgc
726 0 : logic dec_tlu_misc_clk_override;
727 0 : logic dec_tlu_ifu_clk_override;
728 0 : logic dec_tlu_lsu_clk_override;
729 0 : logic dec_tlu_bus_clk_override;
730 0 : logic dec_tlu_pic_clk_override;
731 0 : logic dec_tlu_dccm_clk_override;
732 0 : logic dec_tlu_icm_clk_override;
733 :
734 317 : logic dec_tlu_picio_clk_override;
735 :
736 : assign dccm_clk_override = dec_tlu_dccm_clk_override; // dccm memory
737 : assign icm_clk_override = dec_tlu_icm_clk_override; // icache/iccm memory
738 :
739 : // PMP Signals
740 0 : el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES];
741 : logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES];
742 592407 : logic [31:0] pmp_chan_addr [3];
743 0 : el2_pmp_type_pkt_t pmp_chan_type [3];
744 132567 : logic pmp_chan_err [3];
745 :
746 310 : logic [31:1] ifu_pmp_addr;
747 110 : logic ifu_pmp_error;
748 592373 : logic [31:0] lsu_pmp_addr_start;
749 162421 : logic lsu_pmp_error_start;
750 592411 : logic [31:0] lsu_pmp_addr_end;
751 162421 : logic lsu_pmp_error_end;
752 1059513 : logic lsu_pmp_we;
753 1418396 : logic lsu_pmp_re;
754 :
755 : // -----------------------DEBUG START -------------------------------
756 :
757 0 : logic [31:0] dbg_cmd_addr; // the address of the debug command to used by the core
758 0 : logic [31:0] dbg_cmd_wrdata; // If the debug command is a write command, this has the data to be written to the CSR/GPR
759 0 : logic dbg_cmd_valid; // commad is being driven by the dbg module. One pulse. Only dirven when core_halted has been seen
760 0 : logic dbg_cmd_write; // 1: write command; 0: read_command
761 0 : logic [1:0] dbg_cmd_type; // 0:gpr 1:csr 2: memory
762 0 : logic [1:0] dbg_cmd_size; // size of the abstract mem access debug command
763 0 : logic dbg_halt_req; // Sticky signal indicating that the debug module wants to start the entering of debug mode ( start the halting sequence )
764 0 : logic dbg_resume_req; // Sticky signal indicating that the debug module wants to resume from debug mode
765 317 : logic dbg_core_rst_l; // Core reset from DM
766 :
767 0 : logic core_dbg_cmd_done; // Final muxed cmd done to debug
768 0 : logic core_dbg_cmd_fail; // Final muxed cmd done to debug
769 307463 : logic [31:0] core_dbg_rddata; // Final muxed cmd done to debug
770 :
771 0 : logic dma_dbg_cmd_done; // Abstarct memory command sent to dma is done
772 0 : logic dma_dbg_cmd_fail; // Abstarct memory command sent to dma failed
773 0 : logic [31:0] dma_dbg_rddata; // Read data for abstract memory access
774 :
775 0 : logic dbg_dma_bubble; // Debug needs a bubble to send a valid
776 0 : logic dma_dbg_ready; // DMA is ready to accept debug request
777 :
778 307463 : logic [31:0] dec_dbg_rddata; // The core drives this data ( intercepts the pipe and sends it here )
779 0 : logic dec_dbg_cmd_done; // This will be treated like a valid signal
780 0 : logic dec_dbg_cmd_fail; // Abstract command failed
781 0 : logic dec_tlu_mpc_halted_only; // Only halted due to MPC
782 0 : logic dec_tlu_dbg_halted; // The core has finished the queiscing sequence. Sticks this signal high
783 0 : logic dec_tlu_resume_ack;
784 0 : logic dec_tlu_debug_mode; // Core is in debug mode
785 0 : logic dec_debug_wdata_rs1_d;
786 0 : logic dec_tlu_force_halt; // halt has been forced
787 :
788 6117175 : logic [1:0] dec_data_en;
789 5919698 : logic [1:0] dec_ctl_en;
790 :
791 : // PMU Signals
792 408435 : logic exu_pmu_i0_br_misp;
793 2862021 : logic exu_pmu_i0_br_ataken;
794 3444491 : logic exu_pmu_i0_pc4;
795 :
796 885840 : logic lsu_pmu_load_external_m;
797 800177 : logic lsu_pmu_store_external_m;
798 48780 : logic lsu_pmu_misaligned_m;
799 1655073 : logic lsu_pmu_bus_trxn;
800 36414 : logic lsu_pmu_bus_misaligned;
801 0 : logic lsu_pmu_bus_error;
802 67736 : logic lsu_pmu_bus_busy;
803 :
804 613204 : logic ifu_pmu_fetch_stall;
805 5820350 : logic ifu_pmu_ic_miss;
806 744124 : logic ifu_pmu_ic_hit;
807 0 : logic ifu_pmu_bus_error;
808 4424895 : logic ifu_pmu_bus_busy;
809 10245228 : logic ifu_pmu_bus_trxn;
810 :
811 317 : logic active_state;
812 61045677 : logic free_clk;
813 61045677 : logic active_clk;
814 0 : logic dec_pause_state_cg;
815 :
816 0 : logic lsu_nonblock_load_data_error;
817 :
818 1416948 : logic [15:0] ifu_i0_cinst;
819 :
820 : // fast interrupt
821 0 : logic [31:2] dec_tlu_meihap;
822 0 : logic dec_extint_stall;
823 :
824 5460470 : el2_trace_pkt_t trace_rv_trace_pkt;
825 :
826 :
827 4 : logic lsu_fastint_stall_any;
828 :
829 0 : logic [7:0] pic_claimid;
830 0 : logic [3:0] pic_pl, dec_tlu_meicurpl, dec_tlu_meipt;
831 0 : logic mexintpend;
832 0 : logic mhwakeup;
833 :
834 66 : logic dma_active;
835 :
836 :
837 0 : logic pause_state;
838 0 : logic halt_state;
839 :
840 2065572 : logic dec_tlu_core_empty;
841 :
842 : assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
843 :
844 : assign halt_state = o_cpu_halt_status & ~(dma_active | lsu_active);
845 :
846 :
847 : assign active_state = (~(halt_state | pause_state) | dec_tlu_flush_lower_r | dec_tlu_flush_lower_wb) | dec_tlu_misc_clk_override;
848 :
849 : rvoclkhdr free_cg2 ( .clk(clk), .en(1'b1), .l1clk(free_l2clk), .* );
850 : rvoclkhdr active_cg2 ( .clk(clk), .en(active_state), .l1clk(active_l2clk), .* );
851 :
852 : // all other clock headers are 1st level
853 : rvoclkhdr free_cg1 ( .clk(free_l2clk), .en(1'b1), .l1clk(free_clk), .* );
854 : rvoclkhdr active_cg1 ( .clk(active_l2clk), .en(1'b1), .l1clk(active_clk), .* );
855 :
856 :
857 : assign core_dbg_cmd_done = dma_dbg_cmd_done | dec_dbg_cmd_done;
858 : assign core_dbg_cmd_fail = dma_dbg_cmd_fail | dec_dbg_cmd_fail;
859 : assign core_dbg_rddata[31:0] = dma_dbg_cmd_done ? dma_dbg_rddata[31:0] : dec_dbg_rddata[31:0];
860 :
861 : el2_dbg #(.pt(pt)) dbg (
862 : .rst_l(core_rst_l),
863 : .clk(free_l2clk),
864 : .clk_override(dec_tlu_misc_clk_override),
865 :
866 : // AXI signals
867 : .sb_axi_awready(sb_axi_awready_int),
868 : .sb_axi_wready(sb_axi_wready_int),
869 : .sb_axi_bvalid(sb_axi_bvalid_int),
870 : .sb_axi_bresp(sb_axi_bresp_int[1:0]),
871 :
872 : .sb_axi_arready(sb_axi_arready_int),
873 : .sb_axi_rvalid(sb_axi_rvalid_int),
874 : .sb_axi_rdata(sb_axi_rdata_int[63:0]),
875 : .sb_axi_rresp(sb_axi_rresp_int[1:0]),
876 : .*
877 : );
878 :
879 : `ifdef RV_ASSERT_ON
880 : assert_fetch_indbghalt: assert #0 (~(ifu.ifc_fetch_req_f & dec.tlu.dbg_tlu_halted_f & ~dec.tlu.dcsr_single_step_running)) else $display("ERROR: Fetching in dBG halt!");
881 : `endif
882 :
883 : // ----------------- DEBUG END -----------------------------
884 :
885 : assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
886 :
887 : `ifdef RV_USER_MODE
888 :
889 : // Operating privilege mode, 0 - machine, 1 - user
890 841 : logic priv_mode;
891 : // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
892 931 : logic priv_mode_eff;
893 : // Next privilege mode
894 841 : logic priv_mode_ns;
895 :
896 2 : el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
897 :
898 : `endif
899 :
900 : // fetch
901 : el2_ifu #(.pt(pt)) ifu (
902 : .clk(active_l2clk),
903 : .rst_l(core_rst_l),
904 : .dec_tlu_flush_err_wb (dec_tlu_flush_err_r ),
905 : .dec_tlu_flush_noredir_wb (dec_tlu_flush_noredir_r ),
906 : .dec_tlu_fence_i_wb (dec_tlu_fence_i_r ),
907 : .dec_tlu_flush_leak_one_wb (dec_tlu_flush_leak_one_r ),
908 : .dec_tlu_flush_lower_wb (dec_tlu_flush_lower_r ),
909 :
910 : // AXI signals
911 : .ifu_axi_arready(ifu_axi_arready_int),
912 : .ifu_axi_rvalid(ifu_axi_rvalid_int),
913 : .ifu_axi_rid(ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0]),
914 : .ifu_axi_rdata(ifu_axi_rdata_int[63:0]),
915 : .ifu_axi_rresp(ifu_axi_rresp_int[1:0]),
916 :
917 : .*
918 : );
919 :
920 :
921 : assign iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || ifu_iccm_dma_rd_ecc_single_err;
922 : assign iccm_ecc_double_error = ifu_iccm_rd_ecc_double_err;
923 :
924 : el2_dec #(.pt(pt)) dec (
925 : .clk(active_l2clk),
926 : .dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),
927 : .rst_l(core_rst_l),
928 : .*
929 : );
930 :
931 : el2_exu #(.pt(pt)) exu (
932 : .clk(active_l2clk),
933 : .rst_l(core_rst_l),
934 : .*
935 : );
936 :
937 : el2_lsu #(.pt(pt)) lsu (
938 : .clk(active_l2clk),
939 : .rst_l(core_rst_l),
940 : .clk_override(dec_tlu_lsu_clk_override),
941 : .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r),
942 :
943 : // AXI signals
944 : .lsu_axi_awready(lsu_axi_awready_int),
945 : .lsu_axi_wready(lsu_axi_wready_int),
946 : .lsu_axi_bvalid(lsu_axi_bvalid_int),
947 : .lsu_axi_bid(lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0]),
948 : .lsu_axi_bresp(lsu_axi_bresp_int[1:0]),
949 :
950 : .lsu_axi_arready(lsu_axi_arready_int),
951 : .lsu_axi_rvalid(lsu_axi_rvalid_int),
952 : .lsu_axi_rid(lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0]),
953 : .lsu_axi_rdata(lsu_axi_rdata_int[63:0]),
954 : .lsu_axi_rresp(lsu_axi_rresp_int[1:0]),
955 : .lsu_axi_rlast(lsu_axi_rlast_int),
956 :
957 : .*
958 :
959 : );
960 :
961 : assign dccm_ecc_single_error = lsu_dccm_rd_ecc_single_err;
962 : assign dccm_ecc_double_error = lsu_dccm_rd_ecc_double_err;
963 :
964 : el2_pic_ctrl #(.pt(pt)) pic_ctrl_inst (
965 : .clk(free_l2clk),
966 : .clk_override(dec_tlu_pic_clk_override),
967 : .io_clk_override(dec_tlu_picio_clk_override),
968 : .picm_mken (picm_mken),
969 : .extintsrc_req({extintsrc_req[pt.PIC_TOTAL_INT:1],1'b0}),
970 : .pl(pic_pl[3:0]),
971 : .claimid(pic_claimid[7:0]),
972 : .meicurpl(dec_tlu_meicurpl[3:0]),
973 : .meipt(dec_tlu_meipt[3:0]),
974 : .rst_l(core_rst_l),
975 : .*);
976 :
977 : el2_dma_ctrl #(.pt(pt)) dma_ctrl (
978 : .clk(free_l2clk),
979 : .rst_l(core_rst_l),
980 : .clk_override(dec_tlu_misc_clk_override),
981 :
982 : // AXI signals
983 : .dma_axi_awvalid(dma_axi_awvalid_int),
984 : .dma_axi_awid(dma_axi_awid_int[pt.DMA_BUS_TAG-1:0]),
985 : .dma_axi_awaddr(dma_axi_awaddr_int[31:0]),
986 : .dma_axi_awsize(dma_axi_awsize_int[2:0]),
987 : .dma_axi_wvalid(dma_axi_wvalid_int),
988 : .dma_axi_wdata(dma_axi_wdata_int[63:0]),
989 : .dma_axi_wstrb(dma_axi_wstrb_int[7:0]),
990 : .dma_axi_bready(dma_axi_bready_int),
991 :
992 : .dma_axi_arvalid(dma_axi_arvalid_int),
993 : .dma_axi_arid(dma_axi_arid_int[pt.DMA_BUS_TAG-1:0]),
994 : .dma_axi_araddr(dma_axi_araddr_int[31:0]),
995 : .dma_axi_arsize(dma_axi_arsize_int[2:0]),
996 : .dma_axi_rready(dma_axi_rready_int),
997 :
998 : .*
999 : );
1000 :
1001 : assign pmp_chan_addr[0] = {ifu_pmp_addr, 1'b0};
1002 : assign pmp_chan_type[0] = EXEC;
1003 : assign ifu_pmp_error = pmp_chan_err[0];
1004 : assign pmp_chan_addr[1] = lsu_pmp_addr_start;
1005 : assign pmp_chan_type[1] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
1006 : assign lsu_pmp_error_start = pmp_chan_err[1];
1007 : assign pmp_chan_addr[2] = lsu_pmp_addr_end;
1008 : assign pmp_chan_type[2] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
1009 : assign lsu_pmp_error_end = pmp_chan_err[2];
1010 :
1011 : el2_pmp #(
1012 : .PMP_CHANNELS(3),
1013 : .pt(pt)
1014 : ) pmp (
1015 : .clk (active_l2clk),
1016 : .rst_l(core_rst_l),
1017 : .*
1018 : );
1019 :
1020 : if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB
1021 :
1022 : // AXI4 -> AHB Gasket for LSU
1023 : axi4_to_ahb #(.pt(pt),
1024 : .TAG(pt.LSU_BUS_TAG)) lsu_axi4_to_ahb (
1025 :
1026 : .clk(free_l2clk),
1027 : .free_clk(free_clk),
1028 : .rst_l(core_rst_l),
1029 : .clk_override(dec_tlu_bus_clk_override),
1030 : .bus_clk_en(lsu_bus_clk_en),
1031 : .dec_tlu_force_halt(dec_tlu_force_halt),
1032 :
1033 : // AXI Write Channels
1034 : .axi_awvalid(lsu_axi_awvalid),
1035 : .axi_awready(lsu_axi_awready_ahb),
1036 : .axi_awid(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]),
1037 : .axi_awaddr(lsu_axi_awaddr[31:0]),
1038 : .axi_awsize(lsu_axi_awsize[2:0]),
1039 : .axi_awprot(lsu_axi_awprot[2:0]),
1040 :
1041 : .axi_wvalid(lsu_axi_wvalid),
1042 : .axi_wready(lsu_axi_wready_ahb),
1043 : .axi_wdata(lsu_axi_wdata[63:0]),
1044 : .axi_wstrb(lsu_axi_wstrb[7:0]),
1045 : .axi_wlast(lsu_axi_wlast),
1046 :
1047 : .axi_bvalid(lsu_axi_bvalid_ahb),
1048 : .axi_bready(lsu_axi_bready),
1049 : .axi_bresp(lsu_axi_bresp_ahb[1:0]),
1050 : .axi_bid(lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0]),
1051 :
1052 : // AXI Read Channels
1053 : .axi_arvalid(lsu_axi_arvalid),
1054 : .axi_arready(lsu_axi_arready_ahb),
1055 : .axi_arid(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]),
1056 : .axi_araddr(lsu_axi_araddr[31:0]),
1057 : .axi_arsize(lsu_axi_arsize[2:0]),
1058 : .axi_arprot(lsu_axi_arprot[2:0]),
1059 :
1060 : .axi_rvalid(lsu_axi_rvalid_ahb),
1061 : .axi_rready(lsu_axi_rready),
1062 : .axi_rid(lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0]),
1063 : .axi_rdata(lsu_axi_rdata_ahb[63:0]),
1064 : .axi_rresp(lsu_axi_rresp_ahb[1:0]),
1065 : .axi_rlast(lsu_axi_rlast_ahb),
1066 :
1067 : // AHB-LITE signals
1068 : .ahb_haddr(lsu_haddr[31:0]),
1069 : .ahb_hburst(lsu_hburst),
1070 : .ahb_hmastlock(lsu_hmastlock),
1071 : .ahb_hprot(lsu_hprot[3:0]),
1072 : .ahb_hsize(lsu_hsize[2:0]),
1073 : .ahb_htrans(lsu_htrans[1:0]),
1074 : .ahb_hwrite(lsu_hwrite),
1075 : .ahb_hwdata(lsu_hwdata[63:0]),
1076 :
1077 : .ahb_hrdata(lsu_hrdata[63:0]),
1078 : .ahb_hready(lsu_hready),
1079 : .ahb_hresp(lsu_hresp),
1080 :
1081 : .*
1082 : );
1083 :
1084 : axi4_to_ahb #(.pt(pt),
1085 : .TAG(pt.IFU_BUS_TAG)) ifu_axi4_to_ahb (
1086 : .clk(free_l2clk),
1087 : .free_clk(free_clk),
1088 : .rst_l(core_rst_l),
1089 : .clk_override(dec_tlu_bus_clk_override),
1090 : .bus_clk_en(ifu_bus_clk_en),
1091 : .dec_tlu_force_halt(dec_tlu_force_halt),
1092 :
1093 : // AHB-Lite signals
1094 : .ahb_haddr(haddr[31:0]),
1095 : .ahb_hburst(hburst),
1096 : .ahb_hmastlock(hmastlock),
1097 : .ahb_hprot(hprot[3:0]),
1098 : .ahb_hsize(hsize[2:0]),
1099 : .ahb_htrans(htrans[1:0]),
1100 : .ahb_hwrite(hwrite),
1101 : .ahb_hwdata(hwdata_nc[63:0]),
1102 :
1103 : .ahb_hrdata(hrdata[63:0]),
1104 : .ahb_hready(hready),
1105 : .ahb_hresp(hresp),
1106 :
1107 : // AXI Write Channels
1108 : .axi_awvalid(ifu_axi_awvalid),
1109 : .axi_awready(ifu_axi_awready_ahb),
1110 : .axi_awid(ifu_axi_awid[pt.IFU_BUS_TAG-1:0]),
1111 : .axi_awaddr(ifu_axi_awaddr[31:0]),
1112 : .axi_awsize(ifu_axi_awsize[2:0]),
1113 : .axi_awprot(ifu_axi_awprot[2:0]),
1114 :
1115 : .axi_wvalid(ifu_axi_wvalid),
1116 : .axi_wready(ifu_axi_wready_ahb),
1117 : .axi_wdata(ifu_axi_wdata[63:0]),
1118 : .axi_wstrb(ifu_axi_wstrb[7:0]),
1119 : .axi_wlast(ifu_axi_wlast),
1120 :
1121 : .axi_bvalid(ifu_axi_bvalid_ahb),
1122 : .axi_bready(1'b1),
1123 : .axi_bresp(ifu_axi_bresp_ahb[1:0]),
1124 : .axi_bid(ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0]),
1125 :
1126 : // AXI Read Channels
1127 : .axi_arvalid(ifu_axi_arvalid),
1128 : .axi_arready(ifu_axi_arready_ahb),
1129 : .axi_arid(ifu_axi_arid[pt.IFU_BUS_TAG-1:0]),
1130 : .axi_araddr(ifu_axi_araddr[31:0]),
1131 : .axi_arsize(ifu_axi_arsize[2:0]),
1132 : .axi_arprot(ifu_axi_arprot[2:0]),
1133 :
1134 : .axi_rvalid(ifu_axi_rvalid_ahb),
1135 : .axi_rready(ifu_axi_rready),
1136 : .axi_rid(ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0]),
1137 : .axi_rdata(ifu_axi_rdata_ahb[63:0]),
1138 : .axi_rresp(ifu_axi_rresp_ahb[1:0]),
1139 : .axi_rlast(ifu_axi_rlast_ahb),
1140 : .*
1141 : );
1142 :
1143 : // AXI4 -> AHB Gasket for System Bus
1144 : axi4_to_ahb #(.pt(pt),
1145 : .TAG(pt.SB_BUS_TAG)) sb_axi4_to_ahb (
1146 : .clk(free_l2clk),
1147 : .free_clk(free_clk),
1148 : .rst_l(dbg_rst_l),
1149 : .clk_override(dec_tlu_bus_clk_override),
1150 : .bus_clk_en(dbg_bus_clk_en),
1151 : .dec_tlu_force_halt(1'b0),
1152 :
1153 : // AXI Write Channels
1154 : .axi_awvalid(sb_axi_awvalid),
1155 : .axi_awready(sb_axi_awready_ahb),
1156 : .axi_awid(sb_axi_awid[pt.SB_BUS_TAG-1:0]),
1157 : .axi_awaddr(sb_axi_awaddr[31:0]),
1158 : .axi_awsize(sb_axi_awsize[2:0]),
1159 : .axi_awprot(sb_axi_awprot[2:0]),
1160 :
1161 : .axi_wvalid(sb_axi_wvalid),
1162 : .axi_wready(sb_axi_wready_ahb),
1163 : .axi_wdata(sb_axi_wdata[63:0]),
1164 : .axi_wstrb(sb_axi_wstrb[7:0]),
1165 : .axi_wlast(sb_axi_wlast),
1166 :
1167 : .axi_bvalid(sb_axi_bvalid_ahb),
1168 : .axi_bready(sb_axi_bready),
1169 : .axi_bresp(sb_axi_bresp_ahb[1:0]),
1170 : .axi_bid(sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0]),
1171 :
1172 : // AXI Read Channels
1173 : .axi_arvalid(sb_axi_arvalid),
1174 : .axi_arready(sb_axi_arready_ahb),
1175 : .axi_arid(sb_axi_arid[pt.SB_BUS_TAG-1:0]),
1176 : .axi_araddr(sb_axi_araddr[31:0]),
1177 : .axi_arsize(sb_axi_arsize[2:0]),
1178 : .axi_arprot(sb_axi_arprot[2:0]),
1179 :
1180 : .axi_rvalid(sb_axi_rvalid_ahb),
1181 : .axi_rready(sb_axi_rready),
1182 : .axi_rid(sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0]),
1183 : .axi_rdata(sb_axi_rdata_ahb[63:0]),
1184 : .axi_rresp(sb_axi_rresp_ahb[1:0]),
1185 : .axi_rlast(sb_axi_rlast_ahb),
1186 : // AHB-LITE signals
1187 : .ahb_haddr(sb_haddr[31:0]),
1188 : .ahb_hburst(sb_hburst),
1189 : .ahb_hmastlock(sb_hmastlock),
1190 : .ahb_hprot(sb_hprot[3:0]),
1191 : .ahb_hsize(sb_hsize[2:0]),
1192 : .ahb_htrans(sb_htrans[1:0]),
1193 : .ahb_hwrite(sb_hwrite),
1194 : .ahb_hwdata(sb_hwdata[63:0]),
1195 :
1196 : .ahb_hrdata(sb_hrdata[63:0]),
1197 : .ahb_hready(sb_hready),
1198 : .ahb_hresp(sb_hresp),
1199 :
1200 : .*
1201 : );
1202 :
1203 : //AHB -> AXI4 Gasket for DMA
1204 : ahb_to_axi4 #(.pt(pt),
1205 : .TAG(pt.DMA_BUS_TAG)) dma_ahb_to_axi4 (
1206 : .clk(free_l2clk),
1207 : .rst_l(core_rst_l),
1208 : .clk_override(dec_tlu_bus_clk_override),
1209 : .bus_clk_en(dma_bus_clk_en),
1210 :
1211 : // AXI Write Channels
1212 : .axi_awvalid(dma_axi_awvalid_ahb),
1213 : .axi_awready(dma_axi_awready),
1214 : .axi_awid(dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0]),
1215 : .axi_awaddr(dma_axi_awaddr_ahb[31:0]),
1216 : .axi_awsize(dma_axi_awsize_ahb[2:0]),
1217 : .axi_awprot(dma_axi_awprot_ahb[2:0]),
1218 : .axi_awlen(dma_axi_awlen_ahb[7:0]),
1219 : .axi_awburst(dma_axi_awburst_ahb[1:0]),
1220 :
1221 : .axi_wvalid(dma_axi_wvalid_ahb),
1222 : .axi_wready(dma_axi_wready),
1223 : .axi_wdata(dma_axi_wdata_ahb[63:0]),
1224 : .axi_wstrb(dma_axi_wstrb_ahb[7:0]),
1225 : .axi_wlast(dma_axi_wlast_ahb),
1226 :
1227 : .axi_bvalid(dma_axi_bvalid),
1228 : .axi_bready(dma_axi_bready_ahb),
1229 : .axi_bresp(dma_axi_bresp[1:0]),
1230 : .axi_bid(dma_axi_bid[pt.DMA_BUS_TAG-1:0]),
1231 :
1232 : // AXI Read Channels
1233 : .axi_arvalid(dma_axi_arvalid_ahb),
1234 : .axi_arready(dma_axi_arready),
1235 : .axi_arid(dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0]),
1236 : .axi_araddr(dma_axi_araddr_ahb[31:0]),
1237 : .axi_arsize(dma_axi_arsize_ahb[2:0]),
1238 : .axi_arprot(dma_axi_arprot_ahb[2:0]),
1239 : .axi_arlen(dma_axi_arlen_ahb[7:0]),
1240 : .axi_arburst(dma_axi_arburst_ahb[1:0]),
1241 :
1242 : .axi_rvalid(dma_axi_rvalid),
1243 : .axi_rready(dma_axi_rready_ahb),
1244 : .axi_rid(dma_axi_rid[pt.DMA_BUS_TAG-1:0]),
1245 : .axi_rdata(dma_axi_rdata[63:0]),
1246 : .axi_rresp(dma_axi_rresp[1:0]),
1247 :
1248 : // AHB signals
1249 : .ahb_haddr(dma_haddr[31:0]),
1250 : .ahb_hburst(dma_hburst),
1251 : .ahb_hmastlock(dma_hmastlock),
1252 : .ahb_hprot(dma_hprot[3:0]),
1253 : .ahb_hsize(dma_hsize[2:0]),
1254 : .ahb_htrans(dma_htrans[1:0]),
1255 : .ahb_hwrite(dma_hwrite),
1256 : .ahb_hwdata(dma_hwdata[63:0]),
1257 :
1258 : .ahb_hrdata(dma_hrdata[63:0]),
1259 : .ahb_hreadyout(dma_hreadyout),
1260 : .ahb_hresp(dma_hresp),
1261 : .ahb_hreadyin(dma_hreadyin),
1262 : .ahb_hsel(dma_hsel),
1263 : .*
1264 : );
1265 :
1266 : end
1267 :
1268 : // Drive the final AXI inputs
1269 : assign lsu_axi_awready_int = pt.BUILD_AHB_LITE ? lsu_axi_awready_ahb : lsu_axi_awready;
1270 : assign lsu_axi_wready_int = pt.BUILD_AHB_LITE ? lsu_axi_wready_ahb : lsu_axi_wready;
1271 : assign lsu_axi_bvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_bvalid_ahb : lsu_axi_bvalid;
1272 : assign lsu_axi_bready_int = pt.BUILD_AHB_LITE ? lsu_axi_bready_ahb : lsu_axi_bready;
1273 : assign lsu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bresp_ahb[1:0] : lsu_axi_bresp[1:0];
1274 : assign lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_bid[pt.LSU_BUS_TAG-1:0];
1275 : assign lsu_axi_arready_int = pt.BUILD_AHB_LITE ? lsu_axi_arready_ahb : lsu_axi_arready;
1276 : assign lsu_axi_rvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_rvalid_ahb : lsu_axi_rvalid;
1277 : assign lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_rid[pt.LSU_BUS_TAG-1:0];
1278 : assign lsu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? lsu_axi_rdata_ahb[63:0] : lsu_axi_rdata[63:0];
1279 : assign lsu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rresp_ahb[1:0] : lsu_axi_rresp[1:0];
1280 : assign lsu_axi_rlast_int = pt.BUILD_AHB_LITE ? lsu_axi_rlast_ahb : lsu_axi_rlast;
1281 :
1282 : assign ifu_axi_awready_int = pt.BUILD_AHB_LITE ? ifu_axi_awready_ahb : ifu_axi_awready;
1283 : assign ifu_axi_wready_int = pt.BUILD_AHB_LITE ? ifu_axi_wready_ahb : ifu_axi_wready;
1284 : assign ifu_axi_bvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_bvalid_ahb : ifu_axi_bvalid;
1285 : assign ifu_axi_bready_int = pt.BUILD_AHB_LITE ? ifu_axi_bready_ahb : ifu_axi_bready;
1286 : assign ifu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bresp_ahb[1:0] : ifu_axi_bresp[1:0];
1287 : assign ifu_axi_bid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_bid[pt.IFU_BUS_TAG-1:0];
1288 : assign ifu_axi_arready_int = pt.BUILD_AHB_LITE ? ifu_axi_arready_ahb : ifu_axi_arready;
1289 : assign ifu_axi_rvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_rvalid_ahb : ifu_axi_rvalid;
1290 : assign ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_rid[pt.IFU_BUS_TAG-1:0];
1291 : assign ifu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? ifu_axi_rdata_ahb[63:0] : ifu_axi_rdata[63:0];
1292 : assign ifu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rresp_ahb[1:0] : ifu_axi_rresp[1:0];
1293 : assign ifu_axi_rlast_int = pt.BUILD_AHB_LITE ? ifu_axi_rlast_ahb : ifu_axi_rlast;
1294 :
1295 : assign sb_axi_awready_int = pt.BUILD_AHB_LITE ? sb_axi_awready_ahb : sb_axi_awready;
1296 : assign sb_axi_wready_int = pt.BUILD_AHB_LITE ? sb_axi_wready_ahb : sb_axi_wready;
1297 : assign sb_axi_bvalid_int = pt.BUILD_AHB_LITE ? sb_axi_bvalid_ahb : sb_axi_bvalid;
1298 : assign sb_axi_bready_int = pt.BUILD_AHB_LITE ? sb_axi_bready_ahb : sb_axi_bready;
1299 : assign sb_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_bresp_ahb[1:0] : sb_axi_bresp[1:0];
1300 : assign sb_axi_bid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_bid[pt.SB_BUS_TAG-1:0];
1301 : assign sb_axi_arready_int = pt.BUILD_AHB_LITE ? sb_axi_arready_ahb : sb_axi_arready;
1302 : assign sb_axi_rvalid_int = pt.BUILD_AHB_LITE ? sb_axi_rvalid_ahb : sb_axi_rvalid;
1303 : assign sb_axi_rid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_rid[pt.SB_BUS_TAG-1:0];
1304 : assign sb_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? sb_axi_rdata_ahb[63:0] : sb_axi_rdata[63:0];
1305 : assign sb_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_rresp_ahb[1:0] : sb_axi_rresp[1:0];
1306 : assign sb_axi_rlast_int = pt.BUILD_AHB_LITE ? sb_axi_rlast_ahb : sb_axi_rlast;
1307 :
1308 : assign dma_axi_awvalid_int = pt.BUILD_AHB_LITE ? dma_axi_awvalid_ahb : dma_axi_awvalid;
1309 : assign dma_axi_awid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_awid[pt.DMA_BUS_TAG-1:0];
1310 : assign dma_axi_awaddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_awaddr_ahb[31:0] : dma_axi_awaddr[31:0];
1311 : assign dma_axi_awsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awsize_ahb[2:0] : dma_axi_awsize[2:0];
1312 : assign dma_axi_awprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awprot_ahb[2:0] : dma_axi_awprot[2:0];
1313 : assign dma_axi_awlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_awlen_ahb[7:0] : dma_axi_awlen[7:0];
1314 : assign dma_axi_awburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_awburst_ahb[1:0] : dma_axi_awburst[1:0];
1315 : assign dma_axi_wvalid_int = pt.BUILD_AHB_LITE ? dma_axi_wvalid_ahb : dma_axi_wvalid;
1316 : assign dma_axi_wdata_int[63:0] = pt.BUILD_AHB_LITE ? dma_axi_wdata_ahb[63:0] : dma_axi_wdata;
1317 : assign dma_axi_wstrb_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_wstrb_ahb[7:0] : dma_axi_wstrb[7:0];
1318 : assign dma_axi_wlast_int = pt.BUILD_AHB_LITE ? dma_axi_wlast_ahb : dma_axi_wlast;
1319 : assign dma_axi_bready_int = pt.BUILD_AHB_LITE ? dma_axi_bready_ahb : dma_axi_bready;
1320 : assign dma_axi_arvalid_int = pt.BUILD_AHB_LITE ? dma_axi_arvalid_ahb : dma_axi_arvalid;
1321 : assign dma_axi_arid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_arid[pt.DMA_BUS_TAG-1:0];
1322 : assign dma_axi_araddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_araddr_ahb[31:0] : dma_axi_araddr[31:0];
1323 : assign dma_axi_arsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arsize_ahb[2:0] : dma_axi_arsize[2:0];
1324 : assign dma_axi_arprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arprot_ahb[2:0] : dma_axi_arprot[2:0];
1325 : assign dma_axi_arlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_arlen_ahb[7:0] : dma_axi_arlen[7:0];
1326 : assign dma_axi_arburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_arburst_ahb[1:0] : dma_axi_arburst[1:0];
1327 : assign dma_axi_rready_int = pt.BUILD_AHB_LITE ? dma_axi_rready_ahb : dma_axi_rready;
1328 :
1329 :
1330 : if (pt.BUILD_AHB_LITE == 1) begin
1331 : `ifdef RV_ASSERT_ON
1332 : property ahb_trxn_aligned;
1333 : @(posedge clk) disable iff(~rst_l) (lsu_htrans[1:0] != 2'b0) |-> ((lsu_hsize[2:0] == 3'h0) |
1334 : ((lsu_hsize[2:0] == 3'h1) & (lsu_haddr[0] == 1'b0)) |
1335 : ((lsu_hsize[2:0] == 3'h2) & (lsu_haddr[1:0] == 2'b0)) |
1336 : ((lsu_hsize[2:0] == 3'h3) & (lsu_haddr[2:0] == 3'b0)));
1337 : endproperty
1338 : assert_ahb_trxn_aligned: assert property (ahb_trxn_aligned) else
1339 : $display("Assertion ahb_trxn_aligned failed: lsu_htrans=2'h%h, lsu_hsize=3'h%h, lsu_haddr=32'h%h",lsu_htrans[1:0], lsu_hsize[2:0], lsu_haddr[31:0]);
1340 :
1341 : property dma_trxn_aligned;
1342 : @(posedge clk) disable iff(~rst_l) (dma_htrans[1:0] != 2'b0) |-> ((dma_hsize[2:0] == 3'h0) |
1343 : ((dma_hsize[2:0] == 3'h1) & (dma_haddr[0] == 1'b0)) |
1344 : ((dma_hsize[2:0] == 3'h2) & (dma_haddr[1:0] == 2'b0)) |
1345 : ((dma_hsize[2:0] == 3'h3) & (dma_haddr[2:0] == 3'b0)));
1346 : endproperty
1347 :
1348 :
1349 : `endif
1350 : end // if (pt.BUILD_AHB_LITE == 1)
1351 :
1352 :
1353 : // unpack packet
1354 : // also need retires_p==3
1355 :
1356 : assign trace_rv_i_insn_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_insn_ip[31:0];
1357 :
1358 : assign trace_rv_i_address_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_address_ip[31:0];
1359 :
1360 : assign trace_rv_i_valid_ip = trace_rv_trace_pkt.trace_rv_i_valid_ip;
1361 :
1362 : assign trace_rv_i_exception_ip = trace_rv_trace_pkt.trace_rv_i_exception_ip;
1363 :
1364 : assign trace_rv_i_ecause_ip[4:0] = trace_rv_trace_pkt.trace_rv_i_ecause_ip[4:0];
1365 :
1366 : assign trace_rv_i_interrupt_ip = trace_rv_trace_pkt.trace_rv_i_interrupt_ip;
1367 :
1368 : assign trace_rv_i_tval_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_tval_ip[31:0];
1369 :
1370 :
1371 :
1372 : endmodule // el2_veer
1373 :
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